Chip Industry Technical Paper Roundup: April 23

High-NA EUVL defect inspection; ML-based HW fuzzing; low contact resistance; HW generation languages; 2D vdW magnets above room temp; interface for wide bandgap gate drivers; HW security for heterogeneous integration.


New technical papers recently added to Semiconductor Engineering’s library.

Technical Paper Research Organizations
Approach to Low Contact Resistance Formation on Buried Interface in Oxide Thin-Film Transistors: Utilization of Palladium-Mediated Hydrogen Pathway Tokyo Institute of Technology and National Institute for Materials Science (NIMS)
Beyond Random Inputs: A Novel ML-Based Hardware Fuzzing TU Darmstadt and Texas A&M University
Towards Improved Semiconductor Defect Inspection for high-NA EUVL based on SEMI-SuperYOLO-NAS KU Leuven, imec, Ghent University, and SCREEN SPE
Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration University of Florida (Gainesville)
The Argument for Meta-Modeling-Based Approaches Hardware Generation Languages Infineon Technologies and TU Munich
Field-free deterministic switching of all–van der Waals spin-orbit torque system above room temperature MIT, with funding by the NSF and U.S. Department of Energy
A Three-Channel Package-Scale Galvanic Isolation Interface for Wide Bandgap Gate Drivers STMicroelectronics and DIEEI, Università di Catania

Find last week’s technical paper additions here.

Leave a Reply

(Note: This name will be displayed publicly)