Power Sub-Mesh Construction To Mitigate IR Drop And Minimize Routing Overhead (Intel)


A new technical paper titled "Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability Optimization" was published by researchers at Intel Corporation and National Taiwan University. Abstract: "Multiple power domain design is prevalent for achieving aggressive power savings. In such design, power delivery to cross-domain cells poses a tough challenge at adv... » read more

Chip Industry Technical Paper Roundup: Feb. 6


New technical papers added to Semiconductor Engineering’s library this week. [table id=187 /] More ReadingTechnical Paper Library home » read more

Chip Industry’s Technical Paper Roundup: October 31


New technical papers added to Semiconductor Engineering’s library this week. [table id=159 /] More Reading Technical Paper Library home » read more

Progress In The Fabrication Of CMOS Devices Based On Stacked 2D TMD Nanoribbons (Intel)


A technical paper titled “Process integration and future outlook of 2D transistors” was published by researchers at Intel Corporation. Abstract: "The academic and industrial communities have proposed two-dimensional (2D) transition metal dichalcogenide (TMD) semiconductors as a future option to supplant silicon transistors at sub-10nm physical gate lengths. In this Comment, we share the r... » read more

Chip Industry Technical Paper Roundup: August 15


New technical papers added to Semiconductor Engineering’s library this week. [table id=128 /] More Reading Technical Paper Library home » read more

Modification Of An Existing E-Graph Based RTL Optimization Tool As A Formal Verification Assistant


A technical paper titled “Datapath Verification via Word-Level E-Graph Rewriting” was published by researchers at Intel Corporation and Imperial College London. Abstract: "Formal verification of datapath circuits is challenging as they are subject to intense optimization effort in the design phase. Industrial vendors and design companies deploy equivalence checking against a golden or exi... » read more

Embedded GPU for FPGA, Achieving Over 770 MHz Operating Frequency With Unconstrained Compile


A technical paper titled “eGPU: A 750 MHz Class Soft GPGPU for FPGA” was published by researchers at Intel Corporation and Imperial College London. Abstract: "This paper introduces the eGPU, a SIMT soft processor designed for FPGAs. Soft processors typically achieve modest operating frequencies, a fraction of the headline performance claimed by modern FPGA families, and obtain correspondi... » read more

Chip Industry’s Technical Paper Roundup: July 18


New technical papers recently added to Semiconductor Engineering’s library: [table id=118 /] (more…) » read more

System Level Power Integrity Verification For Multi-Core Microprocessors With FIVR


A technical paper titled "A Compressed Multivariate Macromodeling Framework for Fast Transient Verification of System-Level Power Delivery Networks" was published by researchers at Politecnico di Torino and Intel Corporation. Abstract: This paper discusses a reduced-order modeling and simulation approach for fast transient power integrity verification at full system level. The reference str... » read more

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