tag: interconnects

Is This The Year Of The Chiplet?
By Ed Sperling - 23 Jan, 2020 - Comments: 2

Customizing chips by choosing pre-characterized — and most likely hardened IP — from a menu of options appears to be gaining ground. It's rare to go to a conference these days without hearing chiplets being mentioned. At a time when end markets are splintering and more designs are unique, chiplets are viewed as a way to rapidly build a device using exactly what is required for a particul... » read more

5/3nm Wars Begin
By Mark LaPedus - 23 Jan, 2020 - Comments: 6

Several foundries are ramping up their new 5nm processes in the market, but now customers must decide whether to design their next chips around the current transistor type or move to a different one at 3nm and beyond. The decision involves the move to extend today’s finFETs to 3nm, or to implement a new technology called gate-all-around FETs (GAA FETs) at 3nm or 2nm. An evolutionary step f... » read more

Chiplets, Faster Interconnects, More Efficiency
By Ed Sperling - 22 Aug, 2019 - Comments: 1

Big chipmakers are turning to architectural improvements such as chiplets, faster throughput both on-chip and off-chip, and concentrating more work per operation or cycle, in order to ramp up processing speeds and efficiency. Taken as a whole, this represents a significant shift in direction for the major chip companies. All of them are wrestling with massive increases in processing demands ... » read more

Process Modeling Exploration for 8 nm Half-Pitch Interconnects
By Coventor - 17 Jul, 2019 - Comments: 0

In this paper, we simulate eSADP, eSAQP and iSAOP patterning options to enable fabrication of 8 nm Half-Pitch (HP) interconnects. We investigate the impact of process variations and patterning sensitivities on pitch walking and resistance performance. The overall yield is also calculated for eight line CDs as well as M2-via-M1 via segment resistance and compared for all options. Process sensiti... » read more

Sidestepping Moore’s Law
By Mark LaPedus - 20 Jun, 2019 - Comments: 2

Calvin Cheung, vice president of engineering at ASE, sat down with Semiconductor Engineering to talk about advanced packaging, the challenges involved with the technology, and the implications for Moore’s Law. What follows are excerpts of that conversation. SE: What are some of the big issues with IC packaging today? Cheung: Moore’s Law is slowing down, but transistor scaling will co... » read more

5 Observations From Intel’s Event
By Mark LaPedus - 17 Dec, 2018 - Comments: 0

Not long ago, Intel hosted its “Architecture Day,” where top executives from the chip giant revealed the company’s latest products and next-generation technologies. The company also discussed its strategy. To be sure, it’s a critical time for Intel. In June, Brian Krzanich was forced out as chief executive and the company is still looking for a permanent CEO. Plus, Intel has delayed it... » read more

Accurate, fast P2P resistance extraction for unconventional geometries
By Mentor, a Siemens Business - 12 Dec, 2018 - Comments: 0

Accurately measuring interconnect resistance is fundamental to ensuring circuit reliability. Applications that use unconventional metal structures and multiple probe points require enhanced fracturing techniques to extract P2P resistance quickly and accurately. To read more, click here. » read more

The Case For Chiplets
By Ed Sperling - 10 Dec, 2018 - Comments: 0

Kandou’s Amin Shokrollahi looks at what’s behind the momentum for a LEGO-like approach, where the challenges are, and how the cost compares with other approaches. https://youtu.be/7QHEeagdLzk     ___________________________________ Find more tech talk videos here .   » read more

Die-To-Die Interconnects For Chip Disaggregation
By Mondeep Thiara - 09 Nov, 2018 - Comments: 0

Today, data growth is at an unprecedented pace. We’re now looking at petabytes of data moving into zettabytes. What that translates to is the need for considerably more compute power and much more bandwidth to process all that data. In networking, high-speed SerDes PHYs represent the linchpin for blazing fast back and forth transmission of data in data centers. In turn, demand is increasin... » read more

The Materials Side Of AI
By Jonathan Bakke - 16 Aug, 2018 - Comments: 0

As we enter the foundry 7nm and below technology nodes, tungsten fill for contacts has reached the physical limits of scaling and copper used in the lowest level interconnects is facing challenges on multiple fronts. Solving these issues will require a new conducting material, namely cobalt. This transition can enable continued device scaling and less power consumption per computation. Follo... » read more

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