tag: interposers

Noise Abatement
By Brian Bailey - 12 Oct, 2017 - Comments: 0

[getkc id="285" kc_name="Noise"] is a fact of life. Almost everything we do creates noise as a by-product and quite often what is a signal to one party is noise to another. Noise cannot be eliminated. It must be managed. But is noise becoming a larger issue in chips as the technology nodes get smaller and packaging becomes more complex? For some, the answer is a very strong yes, while for ot... » read more

Packaging Enters New Phase
By Ed Sperling - 07 Aug, 2017 - Comments: 0

The race is on to make advanced packaging less expensive than shrinking everything down onto the same die—much less expensive, in fact. Following several years of speculation and rather shaky market predictions at the beginning of this decade, packaging houses and foundries spent the last four years proving that packaging really does provide a viable alternative to shrinking die in terms o... » read more

Challenges For Future Fan-Outs
By Mark LaPedus - 07 Jul, 2017 - Comments: 1

The fan-out wafer-level packaging market is heating up. At the high end, for example, several packaging houses are developing new fan-out packages that could reach a new milestone and hit or break the magic 1µm line/space barrier. But the technology presents some challenges, as it may require more expensive process flows and equipment like lithography. Fig. 1: Redistribution layers. Source: L... » read more

2.5D Adds Test Challenges
By Jeff Dorsch - 06 Mar, 2017 - Comments: 0

OSATs and ATE vendors are making progress in determining what works and what doesn't in 2.5D packaging, expanding their knowledge base as this evolves into a mainstream technology. A [getkc id="82" kc_name="2.5D"] package generally includes an ASIC connected to a stack of memory chips—usually high-bandwidth memory—using an [getkc id="204" kc_name="interposer"] or some type of silicon bri... » read more

Electrothermal Mechanical Stress Reference Design Flow For Printed Circuit Boards And Electronic Packages
By Ansys - 08 Feb, 2017 - Comments: 0

This paper presents a reference design flow for solving the electrical, thermal and mechanical challenges of a printed circuit board (PCB) using simulation tools from ANSYS. This approach can be utilized for all electrical CAD (ECAD) types such as IC packages, touch panel displays, and glass and silicon interposers. The authors followed this reference design flow for analyzing a PCB virtual pro... » read more

More Degrees Of Freedom
By Ed Sperling - 06 Feb, 2017 - Comments: 0

Ever since the publication of Gordon Moore's famous observation in 1965, the semiconductor industry has been laser-focused on shrinking devices to their practical, and more recently, impractical limit. Increasing transistor density has encountered a number of problems along the way, but it also has enabled us to put computers—which once filled specially built rooms—onto the desktop firs... » read more

Stacked Die Changes
By Ed Sperling - 21 Sep, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. ... » read more

Stacked Die Changes
By Ed Sperling - 15 Sep, 2016 - Comments: 1

Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. ... » read more

The Future Of Memory (Part 2)
By Ed Sperling - 13 Jul, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss future memory with Frank Ferro, senior director of product management for memory and interface IP at [getentity id="22671" e_name="Rambus"]; Marc Greenberg, director of product marketing at [getentity id="22035" e_name="Synopsys"]; and Lisa Minwell, [getentity id="22242" e_name="eSilicon"]'s senior director of IP marketing. What follows are excerpt... » read more

End Of Mixed Signal Engineering?
By Ed Sperling - 04 May, 2016 - Comments: 1

EDA companies are stepping back after years of trying to force engineers to combine analog and digital disciplines. Rather than emphasizing [getkc id="38" kc_name="mixed signal"] as a single expertise, they are building bridges and translation mechanisms between the two worlds. The moves cap more than a decade of trying to find optimal ways to pack [getkc id="37" kc_name="analog"] and digita... » read more

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