tag: interposers

The Race To Mass Customization
By Ed Sperling - 09 Apr, 2018 - Comments: 0

The number of advanced packaging options continues to rise. The choices now include different materials for interposers, at least a half-dozen fan-outs, not to mention hybrid fan-out/3D stacking, system-in-package, flip-chip and die-to-die bridges. There are several reasons for all of this activity. First, advanced packaging offers big improvements in performance and power that cannot be ac... » read more

Cheaper Packaging Options Ahead
By Ed Sperling - 05 Feb, 2018 - Comments: 0

Lower-cost packaging options and interconnects are either under development or just being commercialized, all of which could have a significant impact on the economics of advanced packaging. By far, the most cited reason why companies don't adopt advanced [getkc id="27" kc_name="packaging"] is cost. Currently, silicon [getkc id="204" kc_name="interposers"] add about $30 to the price of a med... » read more

Warp Speed Ahead
By Ed Sperling - 11 Jan, 2018 - Comments: 3

The computing world is on a tear, but not just in one direction. While battery-powered applications are focused on extending the time between charges or battery replacements, there is a whole separate and growing market for massive improvements in speed. Ultimately, this is where quantum computing will play a role, probably sometime in the late 2020/early 2030 timeframe, according to multipl... » read more

Advanced Packaging Still Not So Simple
By Ed Sperling - 08 Jan, 2018 - Comments: 1

The promise of advanced packaging comes in multiple areas, but no single packaging approach addresses all of them. This is why there is still no clear winner in the packaging world. There are clear performance benefits, because the distance between two chips in a package can be significantly shorter than the distance that signals have to travel from one side of a die to another. Moreover, wi... » read more

What’s What In Advanced Packaging
By Choon Lee - 16 Nov, 2017 - Comments: 5

Ever open the body of your smartphone (perhaps unintentionally) and see small, black rectangles stuck on a circuit board? Those black rectangles are packaged chips. The external chip structure protects the fragile integrated circuits inside, as well as dissipates heat, keeps chips isolated from each other, and, importantly, provides connection to the circuit board and other elements. The manufa... » read more

Noise Abatement
By Brian Bailey - 12 Oct, 2017 - Comments: 0

[getkc id="285" kc_name="Noise"] is a fact of life. Almost everything we do creates noise as a by-product and quite often what is a signal to one party is noise to another. Noise cannot be eliminated. It must be managed. But is noise becoming a larger issue in chips as the technology nodes get smaller and packaging becomes more complex? For some, the answer is a very strong yes, while for ot... » read more

Packaging Enters New Phase
By Ed Sperling - 07 Aug, 2017 - Comments: 0

The race is on to make advanced packaging less expensive than shrinking everything down onto the same die—much less expensive, in fact. Following several years of speculation and rather shaky market predictions at the beginning of this decade, packaging houses and foundries spent the last four years proving that packaging really does provide a viable alternative to shrinking die in terms o... » read more

Challenges For Future Fan-Outs
By Mark LaPedus - 07 Jul, 2017 - Comments: 1

The fan-out wafer-level packaging market is heating up. At the high end, for example, several packaging houses are developing new fan-out packages that could reach a new milestone and hit or break the magic 1µm line/space barrier. But the technology presents some challenges, as it may require more expensive process flows and equipment like lithography. Fig. 1: Redistribution layers. Source: L... » read more

2.5D Adds Test Challenges
By Jeff Dorsch - 06 Mar, 2017 - Comments: 0

OSATs and ATE vendors are making progress in determining what works and what doesn't in 2.5D packaging, expanding their knowledge base as this evolves into a mainstream technology. A [getkc id="82" kc_name="2.5D"] package generally includes an ASIC connected to a stack of memory chips—usually high-bandwidth memory—using an [getkc id="204" kc_name="interposer"] or some type of silicon bri... » read more

Electrothermal Mechanical Stress Reference Design Flow For Printed Circuit Boards And Electronic Packages
By Ansys - 08 Feb, 2017 - Comments: 0

This paper presents a reference design flow for solving the electrical, thermal and mechanical challenges of a printed circuit board (PCB) using simulation tools from ANSYS. This approach can be utilized for all electrical CAD (ECAD) types such as IC packages, touch panel displays, and glass and silicon interposers. The authors followed this reference design flow for analyzing a PCB virtual pro... » read more

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