Advanced Packaging Still Not So Simple

While different packaging approaches do improve performance with less power, they still require a lot of advanced engineering.


The promise of advanced packaging comes in multiple areas, but no single packaging approach addresses all of them. This is why there is still no clear winner in the packaging world.

There are clear performance benefits, because the distance between two chips in a package can be significantly shorter than the distance that signals have to travel from one side of a die to another. Moreover, with advanced packaging, those signals can be channeled through hundreds or even thousands of through-silicon vias rather than skinny wires that have been shrunk alongside all of the other components in a 10/7nm chip.

By adding an expensive interposer—or a low-cost bridge, which is what a number of vendors are leaning toward—the performance improvements can be sizeable. That affects the power budget, as well, because it takes less energy to drive a signal over shorter distances. Moreover, because there are more and bigger conduits for electrons, that can be accomplished with less resistance over standard copper. This is why most of the 2.5D chip architectures so far are being used in high-performance computing or networking, where the extra design costs are insignificant compared to the overall system.

Fan-outs are evolving alongside of 2.5D, and increasingly they’re blurring the lines between what’s possible in 2.5D and what used to be the equivalent of a compressed PCB inside a package. Numerous industry sources report experimentation with vertically stacked die in fan-outs, as well as experimentation with faster interconnects. There are even predictions that these two packaging approaches may be comparable in performance and power over time, which will blur the benefits of one versus another.

Monolithic 3D, meanwhile, continues to gain attention in cases where there is a single logic chip, but it has hit so-far insurmountable issues with logic on logic due to heat build-up. There is no simple way to get heat out of the middle of two logic chips sandwiched together in a package without active cooling such as microfluidics. And while this is technically feasible, it’s too complicated and expensive for most applications.

The reason this works in a flip-chip approach—where one chip is literally flipped over on top of another to make contact between the two of them—is because there is no external package to hold in the heat.

All of these approaches help with physical effects such as noise, because it’s easier to layout a design with multiple chips rather than trying to figure out how to shield an analog signal using dielectrics where you can literally count the number of atoms. At 5nm, there will be fewer atoms, and at 3nm still fewer, providing they are on the same chip.

Still, the real promise of advanced packaging involves flexibility, cost reduction and time to market. The idea behind this concept originally was to be able to swap components in and out, depending upon the needs of a particular application or market, without worrying about whether analog IP was developed at 180nm or 40nm, or how noisy the next block is. In short, this was supposed to be simple.

Whether a chiplet approach ultimately can make this work remains to be seen. So far, advanced packaging has proven to be anything but simple. And while it does provide clear power and performance benefits for those willing to spend the time and effort to make it work, it’s not the rapid LEGO block approach that proponents envisioned five years ago. It may be simpler and cheaper than developing a planar chip at 5/3nm, and the form factor may be easier to customize, but the amount of engineering work required is not trivial.

In simple terms, advanced packaging requires advanced engineering. And there is no indication that is about to change anytime soon.

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Marco Koelink says:

That’s why it’s called “advanced”….! 🙂

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