tag: IP reuse

Uncertainty Increases About What’s Next
By Ed Sperling - 24 Oct, 2013 - Comments: 0

Across the semiconductor industry, there is a lot of talk about what’s next. Lithography advances have stalled, NRE and mask costs are rising, and complexity is exploding. But unlike the 1 micron wall, which was supposed to be impenetrable, there is no single issue holding back progress. Instead, there are lots of them, most with pricey workarounds, but which together become more complicat... » read more

More Test Needed For Integrated IP
By Ann Mutschler - 26 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler As the use and reuse of design IPs and cores has reached approximately 70% of the content of an SoC, the need for both pre- and post-silicon test has increased. On the pre-silicon side, test comes in the form of verification IP. Driving the addition of more strenuous test approaches on this side is a combination of forces that impact design, noted Tom Hackett, prod... » read more

Experts At The Table: Low-Power Verification
By Ed Sperling - 16 Aug, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss power format changes with Sushma Hoonavera-Prasad, design engineer in Broadcom’s mobile platform group; John Biggs, consultant engineer for R&D and co-founder of ARM; Erich Marschner, product marketing manager at Mentor Graphics; Qi Wang, technical marketing group director at Cadence; and Jeffrey Lee, corporate ap... » read more

Pitfalls In Subsystem Reuse
By Ann Mutschler - 30 May, 2013 - Comments: 0

By Ann Steffora Mutschler IP subsystems provide a ‘divide and conquer’ approach to SoC design by combining multiple IP blocks together to perform individual functions such as audio, graphics or video. The advantage of this approach is that these functions can be tested and verified at the unit level then integrated with the top-level SoC. This also facilitates reuse because each of ... » read more

Reducing Circuitry To Reduce Power
By Ed Sperling - 14 Jun, 2012 - Comments: 0

By Ann Steffora Mutschler Power is at the top of the list of concerns for design teams today. Consequently, engineers are constantly looking at new techniques and architectural approaches to lower and management the power and energy consumption of their devices. This has resulted in some incredible engineering feats, turning parts of a device on and off as needed, applying different volta... » read more

Experts At The Table: Black Belt Power Management
By Ann Mutschler - 14 Jun, 2012 - Comments: 0

By Ann Steffora Mutschler With approximately 80% of SoC content reused from past designs or brought in from internal and external IP sources, a significant part of a design engineer’s job today is writing glue logic and verifying to make sure the integrated system communicates as dictated by the specification. Integration challenges continue to mount with the increasing amount of black ... » read more

Redefining Design Starts
By Ed Sperling - 26 Jan, 2012 - Comments: 0

For the past decade we have been hearing grim tales about the number of design starts shrinking and how that’s hurting EDA. While that makes for sensational headlines, reality is somewhat fuzzier and far less grim. The big shift that’s underway isn’t so much a decline in design starts as a rise in SoCs. But SoCs are never really created from scratch. They’re a combination of commerci... » read more

Design For Configurability
By Ann Mutschler - 17 Mar, 2011 - Comments: 0

I admit it was a bit of a surprise to me to hear from a leading IP provider of the missteps that still befall design teams today as they seek to reuse IP, but it’s a little like rubbernecking. How do you not look? According to Grant Martin, chief scientist at Tensilica, “The biggest thing that people still don’t think about at the beginning of designing some new function is designing i... » read more

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