Week In Review: Design, Low Power


Tools & IP Cadence debuted System-Level Verification IP (System VIP), a suite of tools and libraries for automating SoC testbench assembly, bus and CPU traffic generation, cache-coherency validation, and system performance bottleneck analysis. Tests created using the System VIP solution are portable across Cadence simulation, emulation and prototyping engines and can also be extended to po... » read more

EDA, IP Show Surprising Strength


EDA and IP revenue surged 12.6% in Q2 to $2.78 billion, up from $2.47 billion in the same period in 2019, according to a just-released report. That growth occurred in all regions, as well. What's surprising about the report is just how strong sales were in the midst of the COVID-19 pandemic. "Revenue was up strongly from Q1, and there was enormous growth," said Wally Rhines, executive spo... » read more

112G SerDes Reliability


Priyank Shukla, product marketing manager at Synopsys, digs into 112Gbps SerDes, why it’s important to examine the performance of these devices in the context of a system, what is acceptable channel loss, and how density can affect performance, power and noise. » read more

Deals That Change The Chip Industry


Nvidia's pending $40 billion acquisition of Arm is expected to have a big impact on the chip world, but it will take years before the effects of this deal are fully understood. More such deals are expected over the next couple of years due to several factors — there is a fresh supply of startups with innovative technology, interest rates are low, and market caps and stock prices of buyers ... » read more

Productivity Keeping Pace With Complexity


Designs have become larger and more complex and yet design time has shortened, but team sizes remain essentially flat. Does this show that productivity is keeping pace with complexity for everyone? The answer appears to be yes, at least for now, for a multitude of reasons. More design and IP reuse is using more and larger IP blocks and subsystems. In addition, the tools are improving, and mo... » read more

Industry Pushes For Fab Tool Security Standards


The semiconductor industry is developing new cybersecurity standards for fab equipment in an effort to protect systems from potential cyberattacks, viruses, and IP theft. Two new standards are in the works, which are being formulated under the auspices of the SEMI trade group with leadership from chipmakers and others. Led by Intel and Cimetrix, the first standard deals with malware-free equ... » read more

Understanding The Performance Of Processor IP Cores


Looking at any processor IP, you will find that their vendors emphasize PPA (performance, power & area) numbers. In theory, they should provide a level playing field for comparing different processor IP cores, but in reality, the situation is more complex. Let us consider performance. The first thing to think about is what aspect of performance you care about. Do you care more about the ... » read more

From Cloud To Cloudlets


Cloudlets, or mini-clouds, are starting to roll out closer to the sources of data in an effort to reduce latency and improve overall processing performance. But as this approach gains steam, it also is creating some new challenges involving data distribution, storage and security. The growing popularity of distributed clouds is a recognition that the cloud model has limitations. Sending the ... » read more

Startup Funding: July 2020


A number of semiconductor and design companies took in funding this month, from a mega round for a data center switch maker to seed grants for two Canadian companies and new funding for an IP marketplace. China continues to be a hot area for electric vehicles, with one company raising half a billion for its two models currently in production. For July, we highlight fifteen startups that raised ... » read more

CodaCache: Helping to Break the Memory Wall


As artificial intelligence (AI) and autonomous vehicle systems have grown in complexity, system performance needs have begun to conflict with latency and power consumption requirements. This dilemma is forcing semiconductor engineers to re-architect their system-on-chip (SoC) designs to provide more scalable levels of performance, flexibility, efficiency, and integration. From the edge to data ... » read more

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