tag: IP

EDA, IP Sales Up 8%
By Ed Sperling - 15 Jan, 2018 - Comments: 0

The EDA sector continues to exhibit solid growth, increasing 8% to $2.2262 billion in Q3, up from $2.0937 billion in the same period in 2016, according to the most recent stats from the ESD Alliance Market Statistics Service. The four-quarter moving average was up 11.5%, year over year. While all of the numbers were up, two areas showed extraordinary growth. One involved Japan, which showed ... » read more

Turning Down The Power
By Jeff Dorsch - 11 Jan, 2018 - Comments: 0

Chip and system designers are giving greater weight to power issues these days. But will they inevitably hit a wall in accounting for ultra-low-power considerations? Performance, power, and area are the traditional attributes in chip design. Area was originally the main priority, with feature sizes constantly shrinking according to Moore's Law. Performance was in the saddle for many years. M... » read more

Could Liquid IP Lead To Better Chips? (Part 3)
By Brian Bailey - 09 Jan, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss the benefits that could come from making IP available as abstract blocks instead of RTL implementations with Mark Johnstone, technical director for Electronic Design Automation for [getentity id="22499" e_name="NXP"] Semiconductor; [getperson id="11489" p_name="Drew Wingard"], CTO at [getentity id="22605" e_name="Sonics"]; Bryan Bowyer, director of ... » read more

Mixed-Signal Issues Worse At 10/7nm
By Ann Mutschler - 03 Jan, 2018 - Comments: 1

Despite increasingly difficulty in scaling digital logic to 10/7nm, not all designs at the leading edge are digital. In fact, there are mixed-signal components in designs at almost all nodes down to 10/7nm. This may seem surprising because analog scaling has been an issue since about 90nm, but these are not traditional analog components. Analog IP increasingly includes highly integrated, mix... » read more

Reflection On 2017: Design And EDA
By Brian Bailey - 03 Jan, 2018 - Comments: 0

People love to make predictions, and most of the time they have it easy, but at Semiconductor Engineering, we ask them to look back on the predictions they make each year and to assess how close to the mark they were. We see what they missed and what surprised them. Not everyone accepts our offer to grade themselves, but most have this year. (Part one looked at the predictions associated with s... » read more

Is Verification Falling Behind?
By Brian Bailey - 21 Dec, 2017 - Comments: 1

Every year that [getkc id="74" comment="Moore's Law"] is in effect means that the [getkc id="10" kc_name="verification"] task gets larger and more complex. At one extreme, verification complexity increases at the square of design complexity, but that assumes that every state in the design is usable and unique. On the other hand, verification has not had the luxury that comes with design reuse b... » read more

The Trouble With Models
By Ed Sperling - 20 Dec, 2017 - Comments: 0

Models are becoming more difficult to develop, integrate and utilize effectively at 10/7nm and beyond as design complexity, process variation and physical effects add to the number of variables that need to be taken into account. Modeling is a way of abstracting the complexity in various parts of the semiconductor design, and there can be dozens of models required for complex SoCs. Some are ... » read more

Toward Self-Driving Cars
By Mark Granger - 18 Dec, 2017 - Comments: 0

The automotive market for semiconductors is shifting into high gear. Right now the average car has about $350 worth of semiconductor content, but that is projected to grow another 50% by 2023 as the overall automotive market for semiconductors grows from $35 billion to $54 billion. This strong growth is being driven by the need to develop what we are calling the ‘connected car.’ The ... » read more

Noise At 7nm And Beyond
By Ed Sperling - 14 Dec, 2017 - Comments: 0

The digital and analog worlds always have been very different. Digital engineers see the world in terms of electrons and a well-defined set of numerical values. Their waves are discrete and squared off and their devices are often noisy when they turn on and off. Analog engineers think in terms of quiet, smooth waves, and they are very concerned about anything that can disrupt those waves, such ... » read more

Could Liquid IP Lead To Better Chips?
By Brian Bailey - 13 Dec, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss the benefits that could come from making IP available as abstract blocks instead of RTL implementations with Mark Johnstone, technical director for Electronic Design Automation for [getentity id="22499" e_name="NXP"] Semiconductor; [getperson id="11489" p_name="Drew Wingard"], CTO at [getentity id="22605" e_name="Sonics"]; Bryan Bowyer, director of ... » read more

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