Predictions: Manufacturing, Devices And Companies

New architectures, materials and equipment could have a huge impact on the chip industry.


Some predictions are just wishful thinking, but most of these are a lot more thoughtful. They project what needs to happen for various markets or products to become successful. Those far reaching predictions may not fully happen within 2018, but we give everyone the chance to note the progress made towards their predictions at the end of the year. (See Reflection On 2017: Design And EDA and Manufacturing And Markets.)

Predictions are divided into four posts this year. Part one covered markets and drivers. This part will look at manufacturing, devices and companies and part three will cover methodologies and tools. In addition, the outlook from EDA executives will be provided in a separate post.

As we move beyond , getting the most out of silicon is becoming as important as looking toward new nodes. “2018 will be the takeoff of 28 and 22nm FD-SOI SoC projects,” predicts Graham Bell, vice president of marketing for Uniquify. “Excellent low-power footprint, RF performance, and lower manufacturing cost makes 22nm FD-SOI a real sweet spot for high-volume IoT and smart business and consumer applications.”

Making the smallest devices requires increasing attention to fabrication tools. “The annual E-beam Initiative survey show a clear trend toward inverse lithography technology (ILT) and multi-beam mask writing at the same time,” points out , CEO of D2S. “Whether for complex ILT patterns for multiple patterning of 193i lithography, or for EUV masks, which will have 30nm sub-resolution assist features (SRAFs) soon, multi-beam writing is needed on the mask side at the leading-edge. Survey respondents predict in 2018 a number of clear indications of production use of multi-beam technology for writing masks intended for production wafers – not just for test chips and test masks.”

The eBeam Initiative survey also shows a clear trend toward more data processing needed to enhance mask and wafer printing. “This trend will continue, putting more pressure on turnaround time,” adds Fujimura. “The industry will see increased activity in GPU-acceleration for simulation, image processing and deep learning to help with this problem in 2018.”

Knowing exactly what was manufactured can help get the best out of the silicon. “2018 will see significant adoption of embedded monitoring technologies within the advanced nodes to help IC designers maintain competitiveness, despite increased effects of process variation and gate density,” says Stephen Crosher, CEO for Moortec. “This will be twinned with the evolution of more sophisticated optimization schemes to reduce power, increase throughput and manage device reliability, especially when consider the management of thermal on-chip conditions.”

For those pushing into the smaller nodes, additional challenges have to be overcome. “I predict a continuous increase in internal clock frequencies (e.g. >5GHz) and an increase in demand for higher data rates (e.g. >10Gbps) that will fuel the electromagnetic (EM) crosstalk challenge,” says Magdy Abadir, vice president of corporate marketing for Helic “Parasitic inductance and inductive coupling that were previously safe to ignore can no longer be ignored. The faster the speed, the louder the crosstalk.”

Current SoC design flows ignore the modeling of inductance parasitics and the modeling of magnetic coupling effects. “Placing complex high-speed digital circuitry, analog and RF blocks very close together increases the risk of EM crosstalk, which in turn can adversely impact the behavior or the performance of SoC,” continues Abadir. “The impact of crosstalk is further exacerbated by the decrease in signal voltage levels driven by lower-power trends in today’s SoC applications. Similarly, the use of advanced 2.5D and 3D packaging increases the risk of EM crosstalk by bringing multiple dies and the packaging layers in close proximity.”

Another complication on the packaging front comes from silicon photonics that “will help overcome the limitations of connectivity in data centers through all-optical computing or even quantum computing,” says Rishi Chugh, senior group director for product marketing for USB, PCIe and SerDes, in Cadence‘s IP Group. “Silicon photonics will move connectivity into the terabit era by dramatically increasing data capacity and data transmission speeds, while simultaneously reducing the network’s carbon footprint and the overall cost per bit. Silicon photonics will play a key role in addressing the challenges of energy efficiency and moving to a low-carbon economy.”

Looking further out, Chugh says that “solid-state lighting sources are expected to outperform almost all other sources in terms of efficiency, offering potential energy savings of 50% or even more when used with intelligent light management systems. Standardization and acceptance of silicon photonics within IEEE standards will further accelerate industry adoption and deployment. With advancements in high-speed serial technology, whereby 112Gbps rates can be achieved over a single lane, silicon photonics is becoming a reality and more feasible with acceptable yields.”

Inside the package is being overhauled. “Improvements in packaging technology potentially allow the use of high bandwidth memory (HBM2) with substrates that cost less than silicon interposers,” says Marc Greenberg, group director, product marketing for DDR, HBM, flash/storage and MIPI IP, in Cadence’s IP Group. “This could become reality in 2018. Combined with smaller process geometries, this opens the door for high-performance computing to happen at a much more local level.”

Devices and FPGAs
RISC-V surprised many during 2017. Can it continue? “In 2018, the semiconductor industry will continue to see strong demand for products in new, innovative applications and implementations of free, open architecture design,” says Rick O’Connor, executive director of the RISC-V Foundation. “We’ll see companies leverage open-source architectures for and machine learning applications – such as voice-based services, which are reshaping the way we get information, and autonomous vehicles, which are revolutionizing transportation – in addition to blockchain technology applications, which have the potential to transform the financial sector, the health care industry, and beyond. The possibilities for an open, free architecture are endless, so the industry must be ready to embrace the impact of this ISA, which is rapidly gaining momentum with more than 100 RISC-V ecosystem members and new products shipping regularly across the globe.”

Others agree. “RISC-V will continue to gain market share in new applications looking for the killer app and drive its acceptance,” adds Gregg Recupero, CTO at Performance-IP. “The killer app will not raise RISC-V to heir apparent status, however. That will happen when its tool chain can rival that of Arm. Otherwise, it will continue to be yet another instruction set architecture.”

How much pressure will it put on Arm? “Arm will continue to dominate by a large margin, but RISC-V will become the leading contender,” says , CEO of Flex Logix..

Some trends will continue, even as end markets change. “As we move into 2018, we expect to see MCUs and connectivity solutions in more integrated packages,” says Vikram Gupta, senior vice president at Cypress. “Multi-chip packages that are cost-effective with die-level integration of MCUs and connectivity will drive solutions for different IoT products, targeting more verticals such as home automation, medical and industrial. Delivering the right software architecture with the ability to plug in applications that offer security or other value-add IoT services will become more prevalent.”

As several predicted in the first part of this series, IoT architectures are changing. “These devices will need to have high-performance processing capabilities and intelligence for localized decision making,” adds Gupta. “Connectivity solutions will need to be robust, energy-efficient and reliable, and be able to coexist with other standards as multiple protocols will become even more important. Companies that are successful in doing all of this will be in a great position to capitalize on the IoT wave.”

Decision making often requires multiple types of compute engine. “To maximize compute efficiency, hardware-acceleration technologies will play a key role in edge computers and cloudlets,” adds Mike Fitton, senior director of product planning and business development for Achronix. “Solutions based around programmable hardware rather than processors provide the freedom to optimize data transfers between virtual neurons. Programmable hardware also provides the freedom to accommodate the wider range of tasks that edge computers will be called on to perform.”

This type of solution ranges from very small to very large applications. “The demand for low power, small form factor and low cost FPGA designs continue to grow, especially as it relates to edge computing and edge connectivity,” says Darin Billerbeck, president and CEO of Lattice Semiconductor. “Products at the edge now require smaller form factors and ultra-low power, which are largely influenced by mobile technology. Energy efficiency is critical for artificial intelligence and machine learning, and small FPGAs are capable of delivering up to 1 tera operations per second under 1 watt.”

And we can expect to see more FPGAs getting integrated into the package. “Aerospace/Defense will become the first market to see rapid adoption of eFPGA,” predicts Flex Logix’s Tate. “10% of FPGAs by dollar value are used by Aerospace/Defense applications and integrating eFPGA significantly reduces weight, volume and power. Also, eFPGA can be designed for any US fab, whereas almost all FPGAs today come from Asia. Security of supply is a critical factor for Defense users. The first commercial chips using eFPGA will appear in 2018 and the number of commercial companies evaluating eFPGA technology will increase significantly.”

FPGAs are also likely to see more adoption at the application level. “The ASSP market size will continue to expand due to the advanced SoC FPGAs being offered today,” says Performance-IP’s Recupero. “These devices provide startup to mid-sized companies the ability to quickly and at low risk develop custom hardware normally required for ASIC development.”

“Expect an increased use of custom hardware based on FPGAs for data center application acceleration,” adds , CEO for Mobiveil. “On the storage front, the move from SATA to PCIe NVMe () SSD drives will continue to be big news in 2018 and next-generation storage class memories (SCM) will add another layer to the memory/storage hierarchy.”

Others also expect NVMe to make big strides. , vice president of engineering for IC Manage says that “utilization of NVMe local storage will become mainstream for high performance computing.”

But that does not mean that older memories will be cast out. “DRAM will continue to provide the best cost and density mix for memory in AI and Deep-learning SoCs that employ multiple CPUs and Convolutional Neural Network (CNNs),” says Uniquify’s Bell. “More HBM2/HMC DRAM-based designs will be adopted in 2018 for projects requiring elite performance without breaking the power budget. Mainstream applications will continue to be dominated by proven LPDDR3/4/4x memories. Tensor Processor Unit (TPU) projects delivered and announced in 2017 are using LPDDR4/x memories to achieve 50GB/s transfer rates and this will continue to meet most system requirements.”

And while on the subject of memories, Bell adds that “more field-programmability for SoCs will occur with the wider of adoption of MRAM/eMRAM that provides persistent storage when chips are not powered and with fast write times versus traditional flash.”

Companies and acquisitions
One of the big questions on everyone mind is the continued consolidation within the industry. “In 2018 semiconductor mega mergers will slow down,” says K. Charles Janac, chairman and CEO of ArterisIP. “My prediction is that the Broadcom acquisition of Qualcomm will not happen due to Qualcomm and regulatory opposition. On the other hand, large investments by China’s government in the indigenous semiconductor industry will create numerous semiconductor companies so that the number of companies designing SoCs on a global basis will actually grow.”

“M&A activity will continue as large semiconductor companies consolidate, leaving open opportunities for many more smaller-sized companies,” says Samir Patel, CEO for Sankalp Semiconductor. “As systems houses become more active with chip design, it will become more “just-in-time” or contract design, a similar concept to contract manufacturing. Chip suppliers will find it’s more economical to consolidate variable chip design needs, especially verification and at the backend. The larger chip vendors will focus more on system-level solutions, do more outsourcing and consolidate vendors for their outsourcing needs, as smaller chip vendors ‘buy’ instead of ‘make.’ This will force consolidation among services and small IP companies to focus on one-stop-shop or the vendor with breadth business model.”

What impact will this have on EDA? “A lot of noise will be made around further consolidation among the semiconductor giants in 2018,” says Michiel Ligthart, president and COO at Verific. “I’m not sure who will be the last one standing, but their need for EDA tools will not diminish. In fact, I anticipate even more interest in creating internal-use tools by semiconductor teams to meet requirements not provided by traditional design tools.”

This could lead to different types of partnerships. “As the vertical integration between engineering methods and tools progresses, and systems companies or OEMs need to become more silicon driven, a deeper integration of EDA tools with systems engineering tools will be required,” says , president and CEO of OneSpin Solutions. “This may also have an impact on alliances and M&A activity.”

But consolidation can lead to attrition. “With the numerous mergers and acquisitions, there will an attrition of people who will help spawn a number of startups especially in the realm of the IoT ecosystem, medical devices, personalized DNA testing, machine learning and AI,” says Ranjit Adhikary, VP of marketing at ClioSoft. “With the growing emphasis on AI, we foresee a growth of chips in this area.”

Will the end of the smart phone era have a big impact? “When you look at the data, smartphone shipments in 2017 will be close to 1.6 billion units,” points out Tom Wong, director of business development for the IP Group of Cadence. “At a 10% annual growth rate, an additional 176 million chipsets are expected to be deployed into the smartphone space in 2018. This means that 1.76 billion chipsets will be needed to support smartphone deployment in 2018, assuming 10% growth. This growth will likely be in China, where we see the domestic suppliers taking huge market share – Huawei, OPPO, Vivo and Xiaomi are all now shipping in excess of 100 million units a year. Riding on this success and growth, it is likely that Xiaomi will go public in 2018 with a valuation in excess of $60 billion.”

Related Stories
Predictions: Markets And Drivers
Part 1: What advancements can we expect to see in 2018, which markets will drive the industry, and what are the major challenges that have to be addressed?
Follow The Moving Money
How economic considerations are affecting designs at advanced nodes and across geographies.
The Next 5 Years Of Chip Technology
Experts at the Table, part 1: Scaling logic beyond 5nm; the future of DRAM, 3D NAND and new types of memory; the high cost of too many possible solutions.

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