The Importance Of Metal Stack Compatibility For Semi IP


Every foundry and every node is different, but for every foundry/node there are multiple supported metal stacks. Some chips use a lot more metal layers than others. A common rule of thumb is each metal layer increases wafer cost 10%. So, a chip with 5 more metal layers than another will cost 50%+ more. The most complex, high performance chips, including performance FPGAs, typically use AL... » read more

Keysight Acquires Cliosoft


Keysight announced today that it has acquired Cliosoft, adding IP data management and design data to its EDA portfolio. The deal comes at a time when chip designs are becoming more heterogeneous and customized, making it more difficult to keep track of a growing number of IP assets. What works for one market or sub-market may not be optimal for another. That could include everything from di... » read more

Zero Trust Security In Chip Manufacturing


More equipment vendors and more IP are making the data in a fab much more valuable than in the past, and a potential target for hackers. What’s needed is a different approach to architecting and deploying services and equipment, so breaches can be stopped before they affect other equipment and data, and a better way of sharing data. Brian Buras, production analytics solution architect at Adva... » read more

Importance Of Qualifying IP Revisions


Design intellectual property (IP) is the fundamental building block of the modern system on chip (SoC). As the scale and complexity of SoCs increases, usage of design IP blocks also increases rapidly, as they enable modularization and re-use of design components. As a result, the usage of design IP has grown rapidly in the past decade. An IP data library consists of many views and formats, w... » read more

What Does 2023 Have In Store For Chip Design?


Predictions seem to be easier to make during times of stability, but they are no more correct than at any other period. During more turbulent times, fewer people are courageous enough to allow their opinions to be heard. And yet it is often those views that are more well thought through, and even if they turn out not to be true, they often contain some very enlightening ideas. 2022 saw some ... » read more

EDA, IP Growth Surges Again


EDA tools and IP revenue increased 8.9% in Q3 of 2022 to $3.767 billion, up from $3.458 billion in 2021, according to a just-released report from the ESD Alliance at SEMI. All regions except Japan reported growth, but the numbers were a bit more uneven in Q3 than in recent quarters. For example, total silicon IP dropped 1%, while services revenue grew 20.8%. At the same time, EDA revenue jum... » read more

Adding Differentiating Value And Reducing IP Integration Time for Your SoC


In the most efficient SoC design processes, semiconductor companies design their own, differentiated IP blocks, acquire high-quality third-party IP, configure it in an SoC-optimized way, and integrate all blocks into the SoC infrastructure of clocks, voltage supplies, on-chip buffer memories or registers, and test circuits. The SoC design team defines and drives the SoC-specific implementation ... » read more

Chip Design Shifts As Fundamental Laws Run Out Of Steam


Dennard scaling is gone, Amdahl's Law is reaching its limit, and Moore's Law is becoming difficult and expensive to follow, particularly as power and performance benefits diminish. And while none of that has reduced opportunities for much faster, lower-power chips, it has significantly shifted the dynamics for their design and manufacturing. Rather than just different process nodes and half ... » read more

Raising IP Integration Up A Level


An increase in the number and complexity of IP blocks, coupled with changing architectures and design concerns, are driving up the need for new tools that can enable, automate, and optimize integration in advanced chips and packages. Power, security, verification and a host of other issues are cross-cutting concerns, and they make pure hierarchical approaches difficult. Adding to future comp... » read more

Addressing SRAM Verification Challenges


SureCore Limited is an SRAM IP company based in Sheffield, the United Kingdom, that develops low power memories for current and next generation silicon process technologies. Its award-winning, world-leading, low power SRAM designs are process independent and variability tolerant, making them suitable for a wide range of technology nodes. Two major product families have been announced: PowerM... » read more

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