tag: Jasper Design Automation

Improving LP Verification Efficiency
By Ann Mutschler - 08 May, 2014 - Comments: 1

The addition of low power circuitry can create so many corner cases that many can escape even the best-written testbenches. This has driven the need for so many additional verification cycles to be run that there must be many datacenter managers at semiconductor companies wondering if it is a trick by the power companies to cause an equal amount of power to be consumed by low-power verification... » read more

Formal Verification Of Power-Aware Designs Using JasperGold Low Power Verification App
By Various Writers - 07 May, 2014 - Comments: 1

Power reduction and management methods are now all-pervasive in system-on-chip (SoC) designs. They are used in SoCs targeted at power-critical applications ranging from mobile appliances with limited battery life to big-box electronics that consume large amounts of increasingly expensive power. Power reduction methods are now applied throughout the chip design flow from architectural design, th... » read more

Hiding The Electronic Crumbs
By Ed Sperling - 01 May, 2014 - Comments: 0

Imagine an old Western movie where the posse tracks the outlaws by following footsteps on a dirt trail or looking for broken branches. Now fast forward to the present, where the trail is electronic, the posse is comprised of bad guys, and the loot is frequently encrypted. As any security expert will concede, every security system can be compromised, every chip can be reverse engineered and h... » read more

When Smart Cards Make Sense…
By Ernest Worthman - 01 May, 2014 - Comments: 1

Smart cards, also referred to as hardware tokens, offer one of the highest levels of security within the framework of securable objects. This is for one obvious reason – it is disconnected from the interconnected world. Unlike wireless or hard-wired objects that require online connectivity for functionality, smart cards must be in physical, or near physical contact (contactless that requir... » read more

Securing Chip Data More Critical Than Ever
By Ann Mutschler - 01 May, 2014 - Comments: 0

Everywhere you turn in the mainstream media, it is easy to find stories of security breaches – from Target not adequately protecting customer data to cars allegedly being hacked to hackers themselves showing how easy it is to do what they do. As technology increases in complexity, so do the hackers themselves. This is a problem. As such, chipmakers are increasingly becoming aware of vulner... » read more

The Week In Review: Design
By Ed Sperling - 25 Apr, 2014 - Comments: 0

M&A Cadence announced its intention to acquire Jasper Design Automation, adding formal technology to its roster of verification tools. The purchase price was about $146 million, the $170 million Cadence offered minus the $24 million in cash and equivalents on Jasper’s books. Tools Synopsys rolled out new LPDDR4 IP that offers up to 3.2 Gbps with low power consumption. The company is ... » read more

Does Formal Have You Covered?
By Brian Bailey - 24 Apr, 2014 - Comments: 1

In part one of this roundtable, the panelists talked about the recent changes that have brought formal to the forefront of verification and discussed the challenges that the UVM have brought to formal. In this segment we start exploring those difficulties in more detail and the progress made with integrated coverage. Participating in the panel were Pete Hardee, director of product management fo... » read more

Cadence Gobbles Up Jasper
By Brian Bailey - 21 Apr, 2014 - Comments: 4

2012 was the year that everyone remembers Synopsys going on an acquisition binge, but 2014 will go down as the year that Cadence Design Systems decided that EDA was worth investing in. Rather than placing investment bets outside of its core competence, Cadence bought Forte in February and now adds Jasper Design Automation to its fold. Jasper started life as Tempus Fugit in 1999 and became Ja... » read more

Blog Review: April 16
By Ed Sperling - 16 Apr, 2014 - Comments: 0

Cadence’s Richard Goering attended a workshop on “extreme” scale design automation, which looked at where else EDA tools can be used—such as intelligent traffic lights. At least there are well-defined use cases. Mentor’s Nazita Saye has compiled five predictions from the 1964 New York World’s Fair that are worth revisiting. Three of them came true. Check out the ones that didn’... » read more

Architecting For Efficiency
By Ann Mutschler - 10 Apr, 2014 - Comments: 0

By definition, to be efficient is to perform or function in the best possible manner with the least waste of time and effort; having and using requisite knowledge, skill, and industry. As this relates to SoC design today, achieving the highest level of efficiency is a challenge with many dimensions. Efficiency comes in multiple ways. “One dimension would be power consumption,” said Oz Le... » read more

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