tag: Jasper Design Automation

Pain Management
By Ed Sperling - 10 Apr, 2014 - Comments: 0

In part one of this series, the focus was on overlapping and new pain points in the semiconductor flow, from initial conception of what needs to be in a chip all the way through to manufacturing. Part two looks at how companies are attempting to manage that pain. It’s no secret that [getkc id="81" kc_name="SoC"]s are getting more complicated to design, debug and build, but the complexity i... » read more

User Case Study: Using Formal To Verify Low Power Functionality And Eliminate Unwanted ‘Xs’
By Joseph Hupcey III - 10 Apr, 2014 - Comments: 3

The cynics among us might argue that the addition of low power circuitry is a clever scheme by the energy industry to cause an equal amount of power to be consumed by low power verification as is saved by end-user usage.  As if modern SoC verification wasn’t challenging enough, the addition of low power can create corner cases that can escape even the most well-written UVM testbenches.  Ind... » read more

Post-Silicon Validation Using Formal Analysis
By Various Writers - 09 Apr, 2014 - Comments: 0

Verifying the current generation of complex SoCs requires the best methodology and tools, including the application of high-capacity formal verification technologies throughout the design flow, from architectural exploration to post-silicon debug. We see this last area, post-silicon debug, as an important value delivered by formal technology for design and verification teams who have not employ... » read more

The Week In Review: Design
By Ed Sperling - 04 Apr, 2014 - Comments: 0

Tools Mentor Graphics rolled out a new platform for verification of unknown voltage levels (Xs) at the register transfer and gate levels, fusing together simulation and formal verification under one umbrella. The company says the approach will limit bugs and wasted effort caused by X-optimism and pessimism. Jasper Design Automation unveiled a new tool to verify the sequential functional equ... » read more

Formal Is Set To Overtake Simulation
By Brian Bailey - 27 Mar, 2014 - Comments: 4

There has been a significant psychology change in the area of formal verification over the past couple of years. It’s no longer considered a fringe technology, and it’s no longer considered difficult to use. In fact, it has become a necessary part of the verification process. Semiconductor Engineering sat down with a panel of experts to find out what caused this change and what more we c... » read more

Blog Review: March 19
By Ed Sperling - 19 Mar, 2014 - Comments: 0

ARM’s Diya Soubra has discovered an interesting term in relation to the Internet of Things: Compound Applications. Will that make the IoT more compelling? Mentor’s Colin Walls points to some less obvious reasons for choosing a processor. No. 4 on his list is particularly noteworthy. Synopsys’ Mick Posner has some thoughts about wearable computing prototypes. Check out the top pho... » read more

Know What To Look For
By Ann Mutschler - 13 Mar, 2014 - Comments: 0

With the number of power domains exploding in today’s ICs, it’s extremely difficult to include all different modes of complexity in the verification. “The problem was already challenging enough,” observed Mark Baker, director of product marketing at Atrenta. “Just looking at where SoC design was going was a collection of various IPs, the different communication protocols, the bus ... » read more

Using Formal Verification Across A Spectrum Of Design Applications
By Various Writers - 12 Mar, 2014 - Comments: 0

Chip designers worldwide have told us that Jasper is fundamentally different in how we approach their technical and business problems by delivering a high ROI (return on investment) through the application of advanced formal verification techniques. Our tools address a spectrum of key verification challenges - from getting the architecture unambiguously right, to putting more power in the hands... » read more

Reducing And Optimizing Power
By Ann Mutschler - 03 Mar, 2014 - Comments: 0

While power optimization/reduction techniques such as clock gating do help engineering teams improve designs from a power perspective, more can be done. In fact, there are tools and methodologies under development to incorporate power in a more meaningful way. Part of that involves accurately pinpointing what designers should be looking for. “If you look at academia or research that has... » read more

Blog Review: Feb. 19
By Ed Sperling - 19 Feb, 2014 - Comments: 0

Adding a GUI to an RTOS? It may sound counterintuitive, but Mentor’s Colin Walls looks at why and where they’re being used. Cadence’s Richard Goering infuses some humor into signal integrity, which could definitely use it, courtesy of Eric Bogatin and Henny Youngman. When was the last time you saw a signal integrity engineer rolling on the floor in hysterical laughter? Well, there’s ... » read more

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