tag: JCET

The Week In Review: Manufacturing
By Mark LaPedus - 19 Jan, 2018 - Comments: 0

Market research The SEMI Industry Strategy Symposium (ISS) opened with the theme “Smart, Intuitive & Connected: Semiconductor Devices Transforming the World.” Click here for some of the highlights at ISS. Here are more highlights from ISS. Korea is on a spending spree for fab tools. In total, Samsung and SK Hynix are forecast to invest over $20 billion in fab tools worldwide in 2018... » read more

Packaging Challenges For 2018
By Mark LaPedus - 08 Jan, 2018 - Comments: 0

The IC packaging market is projected to see steady growth this year, amid ongoing changes in the landscape. The outsourced semiconductor assembly and test ([getkc id="83" kc_name="OSAT"]) industry, which provides third-party packaging and test services, has been consolidating for some time. So while sales rising, the number of companies is falling. In late 2017, for example, [getentity id="2... » read more

Fan-Out Wafer Level eWLB Technology As An Advanced System-In-Package Solution
By STATS ChipPAC - 08 Jan, 2018 - Comments: 0

System-in-Package (SiP) technology continues to be essential for higher integration of functional blocks to meet the ever demanding market needs with respect to smaller form factor, lower cost and time to market. A typical SiP incorporates all or some form of Fan-Out Wafer Level packaging, wire bonding or flip chip that serves a multitude of applications such as optoelectronics, RF, power ampli... » read more

Fan-Outs vs. TSVs
By Jeff Dorsch - 13 Dec, 2017 - Comments: 0

Two years ago, at the annual IMAPS conference on 2.5D and 3D chip packaging, the presentations were dominated by talk of fan-out wafer-level packaging. There was almost no talk of through-silicon vias, which previously had been heralded as vital to 2.5D and 3DIC packaging. Fast forward to this month's 3D Architectures for Heterogeneous Integration and Packaging conference in Burlingame, Cali... » read more

Reliability Of Embedded Wafer-Level BGA For Automotive Radar Applications
By STATS ChipPAC - 11 Dec, 2017 - Comments: 0

With shrinking of chip sizes, Wafer Level Chip Scale Packaging (WLCSP) becomes an attractive and holistic packaging solutions with various advantages in comparison to conventional packages, such as Ball Grid Array (BGA) with flipchip or wirebonding. With the advancement of various fan-out (FO) WLPs, it has been proven to be a more optimal, low cost, integrated and reliable solution compared to ... » read more

Shortages Hit Packaging Biz
By Mark LaPedus - 11 Dec, 2017 - Comments: 1

Rising demand for chips is hitting the IC packaging supply chain, causing shortages of select manufacturing capacity, various package types, leadframes and even some equipment. Spot shortages for some IC packages began showing up earlier this year, but the problem has been growing and spreading since then. Supply imbalances reached a boiling point in the third and fourth quarters of this yea... » read more

ASE-SPIL Merger Wins Clearance
By Mark LaPedus - 24 Nov, 2017 - Comments: 0

Advanced Semiconductor Engineering (ASE) and Siliconware Precision Industries (SPIL) have finally received all anti-trust approvals for the proposed and long-awaited merger between the two IC packaging houses. The anti-trust approvals are a big step that clears the way for the creation of a combined ASE-SPIL entity. The ASE-SPIL entity, in turn, will create a powerhouse in the outsourced ... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 10 Nov, 2017 - Comments: 0

Packaging and test A*STAR’s Institute of Microelectronics (IME) has formed a fan-out wafer-level packaging consortium comprising of OSATs, materials vendors, equipment suppliers and others. The group is called the FOWLP Development Line Consortium. As part of the announcement, Singapore’s IME has established a development line to accelerate the development of fan-out. Located in IME’s... » read more

Litho Options For Panel Fan-out
By Mark LaPedus - 06 Nov, 2017 - Comments: 2

Several packaging houses are inching closer to production of panel-level fan-out packaging, a next-generation technology that promises to reduce the cost of today’s fan-out packages. In fact, ASE, Nepes, Samsung and others already have installed the equipment in their panel-level fan-out lines with production slated for 2018 or so. But behind the scenes, panel-level packaging houses contin... » read more

Challenges And Improvement Of Reliability In Advanced Wafer Level Packaging Technology
By STATS ChipPAC - 06 Nov, 2017 - Comments: 0

The number of WLCSP (wafer-level packages) used in semiconductor packaging has experienced significant growth since its introduction in 1998. The growth has been driven primarily by mobile consumer products because of the small form factor and high performance enabled in the package design. And it is also attractive to wearable electronics and IoT products. Although WLCSSP is now a widely ac... » read more

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