tag: JEDEC

Week In Review: Design, Low Power
By Jesse Allen - 31 Jan, 2020 - Comments: 0

Flex Logix uncorked a new EFLX 1K eFPGA core optimized for the needs of customers on TSMC 40nm Ultra Low Power (ULP) and 40nm Low Power (LP) process technologies. It targets customers focused on low cost and power management. Using a cut-down version and the same software of the EFLX 4K, the EFLX 1K Logic core has 368 inputs and 368 outputs with 900 LUT4 equivalent logic capacity. The EFLX 1K D... » read more

Week In Review: Design, Low Power
By Jesse Allen - 17 Jan, 2020 - Comments: 0

Inphi Corporation and Synopsys finalized the acquisition of eSilicon. Synopsys acquired certain IP assets from eSilicon, including TCAMs and multi-port memory compilers, as well as its Interface IP portfolio with High-Bandwidth Interface (HBI) IP and a team of R&D engineers; it did not disclose terms of the deal. Inphi Corporation bought the rest of the company for approximately $216 millio... » read more

Pushing Memory Harder
By Brian Bailey - 14 Oct, 2019 - Comments: 4

In an optimized system, no component is waiting for another component while there is useful work to be done. Unfortunately, this is not the case with the processor/memory interface. Put simply, memory cannot keep up. Accessing memory is slow, and it can consume a significant fraction of the power budget. And the general consensus is this problem is not going away anytime soon, despite effort... » read more

Week In Review: Design, Low Power
By Jesse Allen - 13 Sep, 2019 - Comments: 0

M&A ANSYS will acquire Livermore Software Technology Corp. (LSTC), a provider of explicit dynamics and other advanced finite element analysis technology. Based in Livermore, CA, LSTC was founded in 1987 to commercialize the DYNA3D technology developed at the Lawrence Livermore National Laboratory. DYNA3D became the company's premier product LS-DYNA, a general purpose nonlinear finite eleme... » read more

The Next New Memories
By Mark LaPedus - 15 Aug, 2019 - Comments: 2

Several next-generation memory types are ramping up after years of R&D, but there are still more new memories in the research pipeline. Today, several next-generation memories, such as MRAM, phase-change memory (PCM) and ReRAM, are shipping to one degree or another. Some of the next new memories are extensions of these technologies. Others are based on entirely new technologies or involve ar... » read more

HBM2E: The E Stands for Evolutionary
By Andy Patrizio - 08 Aug, 2019 - Comments: 2

Samsung introduced the first memory products in March that conform to JEDEC’s HBM2E specification, but so far nothing has come to market—a reflection of just how difficult it is to manufacture this memory in volume. Samsung’s new HBM2E (sold under the Flashbolt brand name, versus the older Aquabolt and Flarebolt brands), offers 33% better performance over HBM2 thanks to doubling the de... » read more

DRAM Tradeoffs: Speed Vs. Energy
By Ed Sperling - 31 Jul, 2019 - Comments: 1

Semiconductor Engineering sat down to talk about new DRAM options and considerations with Frank Ferro, senior director of product management at Rambus; Marc Greenberg, group director for product marketing at Cadence; Graham Allan, senior product marketing manager for DDR PHYs at Synopsys; and Tien Shiah, senior manager for memory marketing at Samsung Electronics. What follows are excerpts of th... » read more

Waiting For Chiplet Interfaces
By Brian Bailey - 13 Jun, 2019 - Comments: 0

There aren't many success stories related to chiplets today for a very simple reason—there are few standard interfaces defined for how to connect them. In fact, the only way to use them is to control both sides of the interface with a proprietary interface and protocol. The one exception is the definition of HBM2, which enables large quantities of third-party DRAM to be connected to a logi... » read more

The Importance Of Using The Right DDR SDRAM Memory
By Vadhiraj Sankaranarayanan - 14 Mar, 2019 - Comments: 0

Selecting the right memory technology is often the most critical decision for achieving the optimal system performance. Designers continue to add more cores and functionality to their SoCs; however, increasing performance while keeping power consumption low and silicon footprint small remains a vital goal. DDR SDRAMs, DRAMs in short, meet these memory requirements by offering a dense, high-perf... » read more

Week In Review: Design, Low Power
By Jesse Allen - 22 Feb, 2019 - Comments: 0

Tools OneSpin unveiled a set of formal apps for development and assessment of RISC-V cores. The RISC-V Integrity Verification Solution formalizes the RISC-V ISA in a set of SystemVerilog Assertions to verify compliance for the ISA is met. It provides a formal bug absence core assessment environment for unbounded proofs and systematic discovery of all hidden instructions or unintended side effe... » read more

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