Week In Review: Design, Low Power

eFPGA for TSMC 40nm ULP/LP; antenna array modeling; Universal Flash Storage update; SPICE library.


Flex Logix uncorked a new EFLX 1K eFPGA core optimized for the needs of customers on TSMC 40nm Ultra Low Power (ULP) and 40nm Low Power (LP) process technologies. It targets customers focused on low cost and power management. Using a cut-down version and the same software of the EFLX 4K, the EFLX 1K Logic core has 368 inputs and 368 outputs with 900 LUT4 equivalent logic capacity. The EFLX 1K DSP core has the same number of inputs/outputs but replaces some of the LUTs with DSPs: 10 DSP MACs, pipeline in blocks of 5, with 650 LUT4 equivalent logic capacity. The EFLX1K on TSMC 40nm ULP process will be silicon verified in Q3.

ANSYS debuted new functionalities in its ANSYS 2020 R1 release, including updates in ANSYS HFSS for quickly and accurately modeling antenna arrays, as well as increased solving speed for very large simulations. It also includes the ability to predict and resolve printed circuit board electromagnetic interference and run transient thermal analyses. Other new features include upgrades to Minerva, which allows for simulation and optimization to be connected to larger product lifecycle processes, enhanced simulation process and data management (SPDM), and connection with OptiSlang for evaluation of design alternatives. Mechanical adds more features to better handle complex, highly nonlinear and massively large models, while Fluent adds a simplified and streamlined workflow that sets up simulations 25% faster and a new algebraic interface area density model that accounts for differences in drag and interfacial area.

MoDeCH launched its English language ecommerce site, “Model On! Search,” expanding from Japan. “With Model On! Search, access to design and simulation models is now a one-stop shop where analog designers can obtain the necessary device models individually and on-demand, which will speed up the design process,” said Masanori Shimasue, CEO of MoDeCH Inc. “Offering the industry’s leading model download site for analog simulations will enable customers that are increasingly dependent on simulations performed using PSPICE and LTspice to complete designs with less time while increasing simulation result accuracy.” The library includes over 72,000 SPICE models of transistors, passive components, and ICs, with both free and fee-based models.

JEDEC published the Universal Flash Storage (UFS) version 3.1 standard, JESD220E. Developed for mobile applications and computing systems requiring high performance with low power consumption, UFS 3.1 introduces new features intended to help maximize device performance while minimizing power usage. New updates include a SLC non-volatile cache that amplifies write speed, a new UFS device low power state targeting lower cost systems that share UFS voltage regulators with other functions, and notification when performance is throttled due to high temperatures. An optional new companion standard, JESD220-3: UFS Host Performance Booster (HPB) Extension, has also been published. The HPB extension provides an option to cache the UFS device logical-to-physical address map in the system’s DRAM.

Digital Blocks added to its DMA Controller Verilog IP Core offerings with capabilities to stream video or data to and from memory as well as to and from over PCIe and UDP/IP Network Interfaces. It supports Xilinx and Intel/Altera PCIe IP to transfer video at up to UHD quality.

Deals & Numbers
Cobham Gaisler successfully verified its first RISC-V line of processors, called NOEL-V, using Aldec’s Riviera-PRO for mixed-HDL simulation. The space-grade design includes an advanced 7-stage dual-issue in-order pipeline and provides up to 4.69 CoreMark/MHz. The company cited the tool’s rich VHDL support, advanced debugging and DRC checking capabilities, compile and simulation speed.

Rambus reported fourth quarter 2019 financial results with $59.9 million in total revenue for the quarter, down 12.5% from the fourth quarter last year. On a GAAP basis, the company saw a net loss per share of $0.09 in Q4 2019, compared to a net loss of $0.02 for the same quarter last year. For the whole year, Rambus saw revenue of $224 million, down 3% from 2018. On a GAAP basis, the company saw a net loss of $0.81 per share, compared to net loss of $1.46 per share last year.

Check out upcoming industry events and conferences: FPGA 2020 will be held Feb. 23-25 in Seaside, CA, and includes sessions on deep learning, architectures, tools, and security. DVCon is Mar. 2-5 in San Jose, CA; key topics include formal verification, Portable Stimulus, IP security, intelligent system design, AI and ML-focused verification, 5G verification, UVM strategies, power-aware design and hybrid verification. Plus, nominations for the Marie R. Pistilli Women in EDA award are open; DAC will be co-located with SEMICon West July 19-23, 2020 in San Francisco, CA.

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