Week In Review: Design, Low Power

By Jesse Allen - 31 Jan, 2020 - Comments: 0

Flex Logix uncorked a new EFLX 1K eFPGA core optimized for the needs of customers on TSMC 40nm Ultra Low Power (ULP) and 40nm Low Power (LP) process technologies. It targets customers focused on low cost and power management. Using a cut-down version and the same software of the EFLX 4K, the EFLX 1K Logic core has 368 inputs and 368 outputs with 900 LUT4 equivalent logic capacity. The EFLX 1K D... » read more

Memory Test Challenges, Opportunities

By Jeff Dorsch - 18 Oct, 2017 - Comments: 0

The semiconductor capital equipment market is on fire, and the memory chip test equipment sector is no different. But it is getting much more difficult on the memory side. Memory test vendors are contending with next-generation devices, such as 3D NAND flash memories, HBM2 chips, low-power double-data-rate DRAMs, graphics DRAMs, phase-change memories, magnetoresistive RAMs, and resistive RAM... » read more

Saving Power In A UFS Implementation Leveraging MIPI M-PHY And UniPro

By Synopsys - 07 Jun, 2017 - Comments: 0

The JEDEC Universal Flash Storage (UFS) has become the mobile storage standard of choice for today’s high-end smartphones and tablets mainly due to the specification’s performance and power advantages over other existing solutions. These advantages become critical to meet end users’ requirements for higher responsiveness and increased capabilities. For example, end users expect to transmi... » read more

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Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

tag: universal flash storage

Week In Review: Design, Low Power

Memory Test Challenges, Opportunities

Saving Power In A UFS Implementation Leveraging MIPI M-PHY And UniPro

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