tag: KAIST

A Practical DRAM-Based Multi-Level PIM Architecture For Data Analytics
By Technical Paper Link - 20 Jul, 2023 - Comments: 0

A technical paper titled "Darwin: A DRAM-based Multi-level Processing-in-Memory Architecture for Data Analytics" was published by researchers at Korea Advanced Institute of Science & Technology (KAIST) and SK hynix Inc. Abstract: "Processing-in-memory (PIM) architecture is an inherent match for data analytics application, but we observe major challenges to address when accelerating it usi... » read more

Week In Review: Design, Low Power
By Jesse Allen - 09 Jun, 2023 - Comments: 0

Renesas Electronics completed its acquisition of Panthronics, a fabless company specializing in near-field communication (NFC) wireless products. Renesas has already incorporated Panthronics NFC technology into several solution reference designs for applications such as payment, IoT, asset tracking, and smart meters. The European Commission announced new funding for the semiconductor and mic... » read more

Chip Industry’s Technical Paper Roundup: Jan. 31
By Linda Christensen - 31 Jan, 2023 - Comments: 0

New technical papers added to Semiconductor Engineering’s library. [table id=77 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us posting l... » read more

Efficiently Process Large RM Datasets In Underlying Memory Pool, Disaggregated Over CXL (KAIST)
By Technical Paper Link - 29 Jan, 2023 - Comments: 0

A technical paper titled "Failure Tolerant Training with Persistent Memory Disaggregation over CXL" was published (preprint) by researchers at KAIST and Panmnesia. "TRAININGCXL can efficiently process large-scale recommendation datasets in the pool of disaggregated memory while making training fault tolerant with low overhead," states the paper. Find the technical paper here. or here (IEE... » read more

Chip Industry’s Technical Paper Roundup: Nov. 1
By Linda Christensen - 01 Nov, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=61 /] » read more

L-FinFET Neuron For A Highly Scalable Capacitive Neural Network (KAIST)
By Technical Paper Link - 31 Oct, 2022 - Comments: 0

A new technical paper titled "An Artificial Neuron with a Leaky Fin-Shaped Field-Effect Transistor for a Highly Scalable Capacitive Neural Network" was published by researchers at KAIST (Korea Advanced Institute of Science and Technology). “In commercialized flash memory, tunnelling oxide prevents the trapped charges from escaping for better memory ability. In our proposed FinFET neuron, t... » read more

Technical Paper Round-Up: July 18
By Linda Christensen - 18 Jul, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=33 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit fo... » read more

Research Bits: July 18
By Jesse Allen - 18 Jul, 2022 - Comments: 0

CXL memory disaggregation Researchers from the Korea Advanced Institute of Science and Technology (KAIST) developed a Compute Express Link (CXL) solution for directly accessible, high-performance memory disaggregation that they say significantly improves performance compared to existing remote direct memory access (RDMA)-based memory disaggregation. RDMA enables a host to directly access an... » read more

SW/HW Framework for for GASNet-enabled FPGA Hardware Acceleration Infrastructure
By Technical Paper Link - 14 Jul, 2022 - Comments: 0

Researchers from KAIST and Flapmax published a new technical paper titled "FSHMEM: Supporting Partitioned Global Address Space on FPGAs for Large-Scale Hardware Acceleration Infrastructure." Abstract "By providing highly efficient one-sided communication with globally shared memory space, Partitioned Global Address Space (PGAS) has become one of the most promising parallel computing model... » read more

Technical Paper Round-Up: May 24
By Linda Christensen - 24 May, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week.   [table id=29 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a ... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy