tag: Keysight

Blog Review: June 5
By Jesse Allen - 05 Jun, 2024 - Comments: 0

Cadence's Neelabh Singh provides an overview of the low power entry and exit flows in USB4 Version 2.0 link speed and how they have been simplified by making low power entry uni-directional and removing the need for certain handshakes for low power exit of the re-timers. In a podcast, Siemens' Steph Chavez chats with Daniel Beeker of NXP about the foundational importance of power distributio... » read more

Chip Design Digs Deeper Into AI
By Ann Mutschler - 03 Jun, 2024 - Comments: 0

Growing demand for blazing fast and extremely dense multi-chiplet systems are pushing chip design deeper into AI, which increasingly is viewed as the best solution for sifting through scores of possible configurations, constraints, and variables in the least amount of time. This shift has broad implications for the future of chip design. In the past, collaborations typically involved the chi... » read more

AI For Data Management
By Adam Kovac - 30 May, 2024 - Comments: 0

Data management is becoming a significant new challenge for the chip industry, as well as a brand new opportunity, as the amount of data collected at every step of design through manufacturing continues to grow. Exacerbating the problem is the rising complexity of designs, many of which are highly customized and domain-specific at the leading edge, as well as increasing demands for reliabili... » read more

Embracing The Future: 5G NTN – Satellite Service For The Masses
By Allison Freedman - 30 May, 2024 - Comments: 0

In a world where communication is paramount, access to reliable networks is not just a luxury but a necessity. Traditionally, satellite communications have been reserved for specialized terminals with cumbersome antennas and costly subscription plans. However, with the advent of 5G Non-Terrestrial Networks (NTNs), the landscape of satellite phone availability is undergoing a revolutionary tran... » read more

Trouble Ahead For IC Verification
By Brian Bailey - 30 May, 2024 - Comments: 0

Verification complexity is roughly the square of design complexity, but until recently verification success rates have remained fairly consistent. That's beginning to change. There are troubling signs that verification is collapsing under the load. The first-time success rate fell (see figure 1) in the last survey conducted by Wilson Research, on behalf of Siemens EDA, in 2022. A new survey ... » read more

Considerations to Successfully Integrate Chiplets in Designs
By Keysight - 29 May, 2024 - Comments: 0

Chiplet integration is a promising approach to creating heterogeneous and complex system-on-chips (SoCs) with significant performance, power, scalability, flexibility, and cost benefits. However, chiplet integration also poses substantial design, verification, testing, and packaging challenges, requiring new standards and design methodologies. Electronic design automation (EDA) software and sim... » read more

Blog Review: May 22
By Jesse Allen - 22 May, 2024 - Comments: 0

Cadence's Sree Parvathy introduces Verilog-A, a high-level language that uses modules to describe the structure and behavior of analog systems and enables the top-down system to be defined before the actual transistor circuits are assembled. Siemens' Keith Felton suggests the process of package substrate design is improved by leveraging the collective expertise of multiple design domain spec... » read more

Running More Efficient AI/ML Code With Neuromorphic Engines
By Karen Heyman - 16 May, 2024 - Comments: 0

Neuromorphic engineering is finally getting closer to market reality, propelled by the AI/ML-driven need for low-power, high-performance solutions. Whether current initiatives result in true neuromorphic devices, or whether devices will be inspired by neuromorphic concepts, remains to be seen. But academic and industry researchers continue to experiment in the hopes of achieving significant ... » read more

Blog Review: May 15
By Jesse Allen - 15 May, 2024 - Comments: 0

Cadence's Anika Sunda suggests that RISC-V has opened numerous doors for innovation and believes EDA tools can help bridge the knowledge gap and foster a growing community of RISC-V developers. Synopsys' Alessandra Costa chats with industry experts about challenges facing analog design, what's needed for multi-die designs, and the potential of AI. Siemens' Bill Ji explains why understandi... » read more

How To Calculate The ROI Of Semiconductor IP Management
By Keysight - 15 May, 2024 - Comments: 0

Intellectual property (IP) is a vital asset for technology companies. IP is often a critical factor in the valuation of a company and must be protected from accidental damage, leakage, and other negative consequences of poor handling. In the context of silicon companies that work on building silicon chips, the term IP involves overseeing both internal IP developed by the company itself and exte... » read more

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