Blog Review: April 19


Synopsys' Soren Smidstrup and Kerim Genc explore how materials modeling helps battery designers explore the wide playing field for new battery materials and optimize performance by co-designing the structure and chemistry of new batteries, ultimately shortening development time and cost. Siemens' Stephen Chavez finds that enabling multiple engineers to work simultaneously within the same PCB... » read more

Power Semiconductors: A Deep Dive Into Materials, Manufacturing & Business


Whether you’re the owner of the average smartphone, commuting on trains, or driving around in a Tesla, you use power semiconductor devices every day. In a technology-dependent world, these devices are everywhere, and demand for more types of chips using different materials is growing. In the past, most engineers paid little attention to power semiconductors. They were deemed commodity, off... » read more

Blog Review: March 29


Siemens' Heather George suggests adopting a shift-left strategy for complex designs that integrate multiple dies into a package and examines the challenges and opportunities for performing comprehensive tests on 2.5D and 3D IC designs. Synopsys' Shekhar Kapoor notes that when considering whether a system will perform as intended, techniques that work well for monolithic SoCs may not be as we... » read more

Tech Forecast: Fab Processes To Watch Through 2040


The massive proliferation of semiconductors in more markets, and more applications within those markets, is expected to propel the industry to more than $1 trillion by 2030. But over the next 17 years, semiconductors will reach well beyond the numbers, changing the way people work, how they communicate, and how they measure and monitor their health and well-being. Chips will be the enabling ... » read more

Getting Smarter About Tool Maintenance


Chipmakers have begun to shift to predictive maintenance for process tools, but the hefty investment in analytics and engineering efforts means it will take some time for smart maintenance to become a widespread practice. Semiconductor manufacturers need to maintain a diverse set of equipment to process the flow of wafers, dies, packaged parts, and boards running through factories. OSAT and ... » read more

New Challenges Emerge With High-NA EUV


High numerical aperture EUV exposure systems are coming — as soon as 2025 by some estimates. Though certainly a less profound change than the introduction of extreme ultraviolet lithography, high-NA lithography still brings a new set of challenges for photoresists and related materials. With a higher numerical aperture, photons strike the wafer at a shallower angle. That requires thinner p... » read more

A Comparative Evaluation Of DRAM Bit-Line Spacer Integration Schemes


With decreasing dynamic random-access memory (DRAM) cell sizes, DRAM process development has become increasingly difficult. Bit-line (BL) sensing margins and refresh times have become problematic as cell sizes have decreased, due to an increase in BL parasitic capacitance (Cb). The main factor impacting Cb is the parasitic capacitance between the BL and the node contact (CBL-NC) [1]. To reduce ... » read more

Chip Industry’s Technical Paper Roundup: Mar. 14


New technical papers recently added to Semiconductor Engineering’s library: [table id=86 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

Virtual Process Game To Benchmark Performance of Humans And Computers For Design Of A Semiconductor Fabrication Process


A new technical paper titled "Human–machine collaboration for improving semiconductor process development" was published by researchers at Lam Research. Abstract: "One of the bottlenecks to building semiconductor chips is the increasing cost required to develop chemical plasma processes that form the transistors and memory storage cells These processes are still developed manually using h... » read more

Blog Review: March 1


Siemens EDA's Chris Spear explains the UVM Factory and how it can facilitate collaboration by enabling injection of new features without affecting your team. Cadence's Paul McLellan looks at efforts to ensure chiplets from different companies work together, particularly when the creating companies didn't pre-plan for those specific chiplets to work together, as well as the problems of failur... » read more

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