Chip Industry’s Technical Paper Roundup: August 1

Partitioning decisions for 3D-ICs; automotive lidar; Si photonics; carbon nanotube PUFs; graphene on SiC; 1024-core RISC-V processors; RISC-V for next-gen automotive; virtual wafer process modeling and metrology.


New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
Impact of gate-level clustering on automated system partitioning of 3D-ICs Université libre de Bruxelles and imec
Overcoming the limitations of 3D sensors with wide field of view metasurface-enhanced scanning lidar Université Côte d’Azur and CRHEA
Unlocking the monolithic integration scenario: optical coupling between GaSb diode lasers epitaxially grown on patterned Si substrates and passive SiN waveguides University of Montpellier, Tyndall National Institute, Munster Technological University and Polytechnic University of Bari
CNT-PUFs: Highly Robust and Heat-Tolerant Carbon-Nanotube-Based Physical Unclonable Functions for Stable Key Generation Chemnitz University of Technology, University of Passau, Technical University of Darmstadt, and Fraunhofer Institute for Electronic Nano Systems (ENAS)
Direct synthesis of nanopatterned epitaxial graphene on silicon carbide University of Technology Sydney, Ludwig-Maxilimians Universität München, Monash University, and Imperial College London
Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster ETH Zürich and Università di Bologna
Towards a RISC-V Open Platform for Next-generation Automotive ECUs ETH Zurich and Huawei Research Center (Italy)
Review of virtual wafer process modeling and metrology for advanced technology development Coventor Inc., Lam Research

More Reading
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