Chip Industry Technical Paper Roundup: June 18


New technical papers added to Semiconductor Engineering’s library this week. [table id=234 /] More ReadingTechnical Paper Library home » read more

Efficient TNN Inference on RISC-V Processing Cores With Minimal HW Overhead


A new technical paper titled "xTern: Energy-Efficient Ternary Neural Network Inference on RISC-V-Based Edge Systems" was published by researchers at ETH Zurich and Universita di Bologna. Abstract "Ternary neural networks (TNNs) offer a superior accuracy-energy trade-off compared to binary neural networks. However, until now, they have required specialized accelerators to realize their effic... » read more

Chip Industry’s Technical Paper Roundup: August 1


New technical papers recently added to Semiconductor Engineering’s library: [table id=39 /] More Reading Technical Paper Library home » read more

Implementing Fast Barriers For A Shared-Memory Cluster Of 1024 RISC-V Cores


A technical paper titled “Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster” was published by researchers at ETH Zürich and Università di Bologna. "Synchronization is likely the most critical performance killer in shared-memory parallel programs. With the rise of multi-core and many-core processors, the relative impact on performance and energy overhe... » read more