tag: LEF

Big Payback For Combining Different Types Of Fab Data
By Anne Meixner - 07 Dec, 2021 - Comments: 1

Collecting and combining diverse data types from different manufacturing processes can play a significant role in improving semiconductor yield, quality, and reliability, but making that happen requires integrating deep domain expertise from various different process steps and sifting through huge volumes of data scattered across a global supply chain. The semiconductor manufacturing IC data... » read more

Optimizing Tool Integration Is Essential To Design Success
By James Paris - 22 Dec, 2020 - Comments: 0

By James Paris and Armen Asatryan The relationship between a place and route (P&R) application and the collection of system-on-chip (SoC) design implementation, analysis, and verification methodologies and tools has always been very much a two-way street. The P&R system is the base, if you will, of design implementation—it takes the virtual and makes it physical. However, it is use... » read more

Early Detection Of Power/Ground Shorts Speeds Time To Tapeout
By Mentor, a Siemens Business - 27 May, 2020 - Comments: 0

Early detection of power/ground shorts lets design teams fix errors during implementation, avoiding time-consuming design data merging and full-chip physical verification. The Calibre platform provides fast, automated power/ground checking using abstract LEF/DEF input, significantly reducing the time and resources needed to ensure these violations are removed prior to tapeout. To read more, ... » read more

Enhancing IO Ring Checks For Consistent, Customizable Verification
By Mentor, a Siemens Business - 25 Nov, 2019 - Comments: 0

The Calibre PERC IO ring checker framework eliminates manual checking by providing a robust DRC-like environment to verify all IO placement rules with sign-off quality. Running on the first LEF/DEF floorplan, the IO ring checker provides early and full coverage of IO ring placement rules, enabling changes with minimal impact on the layout. Fast, accurate debugging and correction ensures that So... » read more

Containing Design Complexity With POP IP
By Kelvin Low - 16 Nov, 2018 - Comments: 0

About 25 years ago, Carver Mead, one of the pioneers of VLSI design, told a technical audience then grappling with the complexities of quarter-micron design that he could see an evolutionary path to about 130nm, but after that point, the picture blurred. Flash forward to the present and we’re manufacturing SoCs at 7nm, and the output is truly amazing devices powering applications we and Me... » read more

More Data, Different Approaches
By Ed Sperling - 25 Jun, 2015 - Comments: 0

Scaling, rising complexity, and integration are all contributing to an explosion in data, from initial design to physical layout to verification and into the manufacturing phase. Now the question is what to do with all of that data. For SoC designs, that data is critical for identifying real and potential problems. It also allows verification engineers working the back end of the design flow... » read more

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