Multiple Patterns, Multiple Trade-Offs

By David Abercrombie - 11 Dec, 2014 - Comments: 0

As the saying goes, “There is no such thing as a free lunch.” That is a reality that chip designers have had to live by from the beginning. From the advent of the first design rule, it was clear that you couldn’t just do anything you wanted. In the end, everything comes down to trade-offs. Whether it’s area, speed, leakage, noise sensitivity, or drive current, doing something to impr... » read more

Litho Options Sparse After 10nm

By Mark LaPedus - 16 Oct, 2014 - Comments: 0

Leading-edge foundries are ramping up their 16nm/14nm logic processes, with 10nm and 7nm in R&D. Barring a major breakthrough in [getkc id="80" comment="lithography"], chipmakers will use 193nm immersion and multiple patterning for both 16nm/14nm and 10nm. So now, chipmakers are focusing on the lithography options for 7nm. As before, the options include the usual suspects—[gettech id="... » read more

How Much Multipatterning?

By Ed Sperling - 19 Jun, 2014 - Comments: 2

The latest consensus among litho experts is that extreme ultraviolet (EUV) will appear in the market sometime in coming months in a commercially viable form. The only question is the degree of commercially viability, and what it will actually cost. While some debate lingers about whether EUV will ever get going, the general feeling is that enough progress has been made recently to make it work.... » read more

Self-Aligned Double Patterning, Part One

By David Abercrombie - 15 May, 2014 - Comments: 0

I’m sure most of you have seen a Rorschach test ink blot (Figure 1). Psychiatrists ask the subjects to tell them what they “see” in the ink blot. The answers are used to characterize the respondent’s personality and emotional functioning. I am never sure if I would feel more uncertain being the psychiatrist asking the question, or the subject trying to decide what to say, given there ar... » read more

What If EUV Fails?

By Mark LaPedus - 17 Apr, 2014 - Comments: 2

It’s the worst kept secret in the industry, but extreme ultraviolet (EUV) lithography will likely miss the 10nm node. So, chipmakers will likely extend and use today’s 193nm immersion lithography down to 10nm. This, of course, will require a complex and expensive multiple patterning scheme. Now, chipmakers are formulating their lithography strategies for 7nm and beyond. As it stands now,... » read more

Tech Talk: Multipatterning, Take Two

By Brian Bailey - 31 Mar, 2014 - Comments: 0

Mentor Graphics' David Abercrombie continues with his whiteboard talk about coloring with advanced lithography, including what goes wrong and how to fix it. [youtube vid=HCBtvHCcbf4] » read more

Directed Self-Assembly Gains Momentum

By Mark LaPedus - 20 Mar, 2014 - Comments: 0

At last year’s SPIE Advanced Lithography symposium, directed self-assembly (DSA) grabbed the spotlight as chipmakers provided the first glimpse of their initial work and results with the technology. The results were stunning, thereby propelling DSA from a curiosity item to a possible patterning solution for next-generation devices. Last year, in fact, GlobalFoundries, IBM, Intel and Sams... » read more

When Order Matters

By David Abercrombie - 20 Mar, 2014 - Comments: 0

Do you brush your teeth before dinner? Put on your shoes before going to bed? Iron your clothes before you wash them? Okay, forget that last one. No one irons clothes anymore…do they? Anyway, my point is, if you want to achieve the best results from a process, order can be really important. And so it is with double patterning (DP) error debugging. As I’ve discussed, there are many types ... » read more

What Goes Around Comes Around: Moore’s Law At 10nm And Beyond

By Greg Yeric - 13 Feb, 2014 - Comments: 2

Modified by Greg Yeric from original by Eric Fischer Gordon Moore penned his famous observation in an era when the people developing the process were also the people designing the circuits. Over time, things got more complicated and work specialization set in, but all was well in the world for many years as the fabs kept delivering on Moore’s Law. Yes, designers had to come up with lot... » read more

DFM Challenges Abound Below 20nm

By Ed Sperling - 13 Dec, 2012 - Comments: 0

By Ann Steffora Mutschler As semiconductor design teams struggle to wring the last few percentage of die shrink from a technology node, much of the ability to do that rests on the EDA tools. From place and route through DFM checks—essentially, everything that happens before the design is sent to the fab or foundry—it all must be tightly integrated with the manufacturing process so it co... » read more

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Knowledge Centers
Entities, people and technologies explored

Intel Vs. Samsung Vs. TSMC

Foundry competition heats up in three dimensions and with novel technologies as planar scaling benefits diminish.

by Ed Sperling

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Chip Industry Week In Review

Softbank's acquisition; advanced packaging funding; glass substrates; engineered copper wire; semi equipment set new record; HBM4; AI chips rake in funding; X-ray inspection; apprenticeships.

by The SE Staff

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

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