What If EUV Fails?

193nm immersion lithography probably can be extended to 7nm, but beyond that it may get very expensive.


It’s the worst kept secret in the industry, but extreme ultraviolet (EUV) lithography will likely miss the 10nm node. So, chipmakers will likely extend and use today’s 193nm immersion lithography down to 10nm. This, of course, will require a complex and expensive multiple patterning scheme.

Now, chipmakers are formulating their lithography strategies for 7nm and beyond. As it stands now, EUV and the other next-generation lithography (NGL) tool technologies are not a sure thing for 7nm.

So, lithographers are now asking themselves some tough questions. For example, what if EUV remains delayed at 7nm or fails all together? If so, how far can the industry extend 193nm immersion? And at what cost?

In theory, 193nm immersion could extend to 7nm and beyond, but there is a catch. It may require octuple patterning and other complex steps, which could be an expensive and terrifying proposition. The sheer cost and complexity of this lithographic solution could dissuade chipmakers from jumping to future nodes, thereby stunting the growth rates of the IC industry.

On the other hand, there is another school of thought—193nm immersion, along with multiple patterning, can extend to at least 3nm and do it without bankrupting the industry. “We have only penetrated half way through the immersion ‘s-curve,’ ” said Christopher Bencher, a member of the technical staff at Applied Materials. “What we see happening in immersion lithography is a lot of interactive innovation taking place, which is going to make this technology last much longer than people originally anticipated.”

Bencher’s reference to the “s-curve” is derived from a rate of adoption theory for any new innovation. Originally devised by sociologist Everett Rogers, the rate of adoption model resembles a conventional Bell curve or “s-shaped curve.”

With the help of the emerging multiple patterning schemes, the “s-curve” for 193nm immersion is still moving in an upward trajectory, Bencher said. “We still have a lot of resolution enhancement techniques that are in our tool kit,” he said. “A lot of these have not been implemented yet.”

These techniques, sometimes referred to as 193nm extensions, could even keep lithographic costs within reason. There are several competing technology candidates on the table. They include the traditional multiple exposure schemes. The new kid on the logic block is self-aligned double/quadruple patterning (SADP/SAQP). Another option is directed self-assembly (DSA). And finally, there are several newfangled process-related technologies on the table, such as photoresist dry shrink, self-aligned vias and even an invisible hard mask.

Eventually, chipmakers may end up using more than one technology, but the ultimate goal is clear. “The industry is looking for the cheapest way to do lithography,” said Dean Freeman, an analyst with Gartner.

Optical lithography forever?
Years ago, the International Technology Roadmap for Semiconductors (ITRS) projected that 193nm immersion would hit the wall at 45nm. Then, the industry would insert an NGL, such as EUV, multibeam or nanoimprint.

Clearly, that prediction was wrong. Today, NGL remains delayed and is still not ready, while 193nm immersion has defied physics and remains the workhorse technology in the fab. In reality, though, single-exposure, 193nm lithography reached its physical limit at 40nm half-pitch, but the industry has been able to extend optical by using various resolution enhancement techniques. And starting at the 22nm/20nm logic node, the laws of physics dictate that chipmakers must use optical lithography, plus a multiple patterning scheme.

Cost, complexity and overlay are just a few of the challenges with 193nm immersion and multiple patterning. Generally, using 193nm immersion, the shift from single exposure at 28nm to multiple patterning at 10nm is projected to increase lithography costs by nearly 1.8 times, according to Imec.

On the other hand, Applied’s Bencher has a different viewpoint. “People talk about quad patterning, or even octuple patterning,” he said. “There are people on the street who say, ‘There is no way you can control it in production.’ That’s not what we’ve observed.”

Besides cost, there are two other components in multiple patterning—tool selection and the technology scheme. As before, the two tool vendors, ASML and Nikon, continue to extend 193nm immersion by improving the capabilities of their respective scanners. For example, Nikon recently rolled out the NSR-S630D, a 193nm immersion scanner that has a ≤2.5nm overlay and a throughput of 250 wafers per hour. “These are all essential factors in enabling cost-effective multiple patterning at 10nm and beyond,” said Hamid Zarringhalam, executive vice president of Nikon.

Next, chipmakers must choose between a multitude of multiple patterning schemes for both 193nm immersion and EUV. To make it more complex, each multiple patterning scheme is competing for a different part of the logic structure. In logic, there are four critical pieces that require patterning—fin/act; gate; metal; and via.

Basically, there are two main categories of multiple patterning—pitch splitting and spacer. Pitch splitting includes traditional double patterning, which requires two separate lithography and etch steps to define a single layer. This is often called litho-etch-litho-etch. Double patterning provides a 30% reduction in pitch, according to Sematech. Meanwhile, triple patterning requires three exposures and etch steps. And so on.

Spacer, meanwhile, involves SADP and SAQP. This process uses one lithography step and additional deposition and etch steps to define a spacer-like feature. SADP/SAQP, which have been used to extend NAND to the 1xnm node, is now moving into logic.

Litho strategies
All told, chipmakers will likely use immersion/multiple patterning at 10nm. But at 7nm and beyond, the lithographic roadmap is cloudy. “Beyond 10nm, a lot depends on the schedules,” said Chris Mack, gentleman scientist and a lithography expert. “My personal belief is that the schedules are going to slip because of the difficulties and costs associated with continued litho scaling. One possibility is that the 7nm node slips in terms of its timing. In that case, it opens up the door for more options being ready.”

Today, chipmakers would prefer to insert EUV at 7nm, but there are still uncertainties with the technology. “The requirements for 7nm are much tighter than 10nm. And so, EUV has to shoot for a tighter target, which makes it harder,” Mack said. “193nm is not standing still and is improving over time. That helps multiple patterning to become more cost effective.”

In any case, each chipmaker has its own strategy. Intel, for one, has been embracing a pitch-splitting concept called complementary lithography. “Gradually, we’ve implemented increasingly strict design rules to the point that our layouts are unidirectional,” said Mark Phillips, engineering manager for lithography at Intel. “They have good features. The point is that it is not just beneficial for lithographers, but it’s also beneficial in process control.”

Intel’s concept involves a two-step process—gratings and line cuts—to pattern designs. Up until 7nm, Intel plans to use 193nm immersion to make both the gratings and cuts. Then, at 7nm, 193nm immersion would still be used to make the gratings, while EUV or multibeam would be inserted to make the cuts in order to lower the costs.

But if EUV and multibeam happen to miss the 7nm node, the process becomes more expensive and complex. “If you do (the cuts) with 193nm immersion, you have to split up all of these cuts. So you are looking at a single metal via pattern with nine masks to pattern. I don’t think this is a series of easy steps,” Phillips said.

Others have a different strategy. For example, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) wants to insert EUV at 10nm, but it will likely use 193nm immersion and multiple pattering. “TSMC’s 10nm plan is to use litho-etch-litho-etch for the metal one and via layers and SADP where they can, such as the fins and poly,” lithography expert Mack said. “It is a plan that will work. The only thing that might not work is the economics. We have to wait and see about that.”

At 7nm, there are a multitude of possibilities for chipmakers. In one scenario, Gerry Luk-Pat, senior staff engineer at Synopsys, envisioned the following scheme at 7nm: “For the fin layer, we are going to evolve from self-aligned double to self-aligned quadruple. For metal one, we can stay on triple patterning. For metal two and metal x, we will move from self-aligned double patterning to triple patterning. The trim mask itself will need multiple patterning.”

New solutions
Based on those roadmaps, SADP/SAQP could be the next big thing for multiple patterning in logic. “SADP ended up driving NAND scaling for five technology nodes,” said Applied’s Bencher. “A lot of people thought this technology would hurt costs, but you don’t see any hiccup in the cost reduction slope in NAND.”

The question is whether SADP/SAQP can be applied to logic. “You can make complicated patterns in logic with SADP and SAQP,” Bencher said. “Today, we have a process flow that runs at Imec. We have demonstrated a 22nm dual damascene flow. The question is can you make SADP contacts? In fact, you can. What we’ve seen is that your contact is a rectangular slot. You can have rectangular slots by making a bunch of trenches using SADP and then coming in with a cut mask. You can take this technology down to 40nm pitch contacts. This is really on par with what EUV is trying to do.”

There are some challenges with SADP/SAQP in logic. “The first one is the edge-placement error,” said Intel’s Phillips. “The second is the focus budget. It also turns out that these pattern splits are not a panacea. It tends to drive printed features that are more isolated.”

Besides SADP/SAQP, there are other technologies on the table. One example is a combination spacer-triple pattering scheme. In addition, there are also innovations taking place on the LELE front. “When you are looking at going from a single exposure to litho-etch-litho-etch, it’s going to be complex,” Applied’s Bencher said. “You are going to create some topography from your first litho-etch and then you will have to re-planarize that with a spin-on carbon.”

Looking to simplify the process, Applied has developed a technology called the invisible hard mask. “What we do is take an invisible hard mask and you design that at 193nm to exactly match your photoresist. The index exactly matches and then you have no reflection off the resist interface. Therefore, you make it invisible. And now, you can do the unthinkable. You can do lithography over topography,” Bencher said.

Other technologies, such as DSA, dry shrink, and self-aligned vias, are possible options down the road. In a photoresist dry shrink process, for example, Applied Materials took a resist with a 72nm trench. Using dry 193nm lithography, Applied demonstrated the ability to shrink a structure to 15nm or 10nm with good uniformities.

Implementing some or all of these technologies could solve many problems, but it’s easier said than done. “It’s not simple to say that EUV is not coming and let’s scale with self-align double, triple and quad patterning,” said Ofer Adan, global product manager and a member of the technical staff at Applied Materials. “Certainly, there are going to be challenges.”


The Next Generation Litho Tool Is. . . . . . . .Immersion! | Manufacturing | Mannerisms says:

[…] EUV has so far cost $14 billion, reports Semiconductor Engineering. […]

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