Improving Library Characterization Quality And Runtime With Machine Learning


By Megan Marsh and Wei-Lii Tan Today’s semiconductor applications, ranging from advanced sensory applications, IoT, edge computing devices, high performance computing, to dedicated A.I. chips, are constantly pushing the boundaries of attainable power, performance, and area (PPA) metrics. The race to design and ship these innovative devices has resulted in a focused, time-to-market-driven e... » read more

Next-Generation Liberty Verification And Debugging


Accurate library characterization is a crucial step for modern chip design and verification. For full-chip designs with billions of transistors, timing sign-off through simulation is unfeasible due to run-time and memory constraints. Instead, a scalable methodology using static timing analysis (STA) is required. This methodology uses the Liberty file to encapsulate library characteristics such ... » read more

Addressing Process Variation And Reducing Timing Pessimism At 16nm And Below


At 16nm and below, on-chip variation (OCV) becomes a critically important issue. Increasing process variation makes a larger impact on timing, which becomes more pronounced in low-power designs with ultra-low voltage operating conditions. In this paper, we will discuss how a new methodology involving more accurate library characterization and variation modeling can reduce timing margins in libr... » read more