Searching For EUV Defects

By Mark LaPedus - 19 Apr, 2018 - Comments: 1

Chipmakers hope to insert extreme ultraviolet (EUV) lithography at 7nm and/or 5nm, but several challenges need to be solved before this oft-delayed technology can be used in production. One lingering issue that is becoming more worrisome is how to find defects caused by [gettech id="31045" comment="EUV"] processes. These processes can cause random variations, also known as stochastic effects... » read more

EUV’s New Problem Areas

By Mark LaPedus - 19 Mar, 2018 - Comments: 2

Extreme ultraviolet (EUV) lithography is moving closer to production, but problematic variations—also known as stochastic effects—are resurfacing and creating more challenges for the long-overdue technology. GlobalFoundries, Intel, Samsung and TSMC hope to insert [gettech id="31045" comment="EUV"] lithography into production at 7nm and/or 5nm. But as before, EUV consists of several compo... » read more

What EUV Brings To The Table

By Moshe Preil - 15 Feb, 2018 - Comments: 0

After many years of hearing that EUV is almost ready for prime time, the tide is finally coming in. A decade of slow but steady progress has resulted in exposure tools that can expose on the order of 1,000 wafers a day on a regular basis. This may be shy of the requirements for high volume manufacturing (HVM), but it is certainly more than enough to support solid development programs and pilot ... » read more

Silicon Photonics: Solving Process Variation And Manufacturing Challenges

By Sandy Wen - 17 Aug, 2017 - Comments: 0

As silicon photonics manufacturing gains momentum with additional foundry and 300mm offerings, process variation issues are coming to light. Variability in silicon processing affects the waveguide shape and can result in deviation in effective indices, propagation loss, and coupling efficiency from the intended design. In this article, we will highlight process variation issues that can occur i... » read more

Is 7nm The Last Major Node?

By Ed Sperling - 20 Jul, 2017 - Comments: 3

A growing number of design and manufacturing issues are prompting questions about what scaling will really look like beyond 10/7nm, how many companies will be involved, and which markets they will address. At the very least, node migrations will go horizontally before proceeding numerically. There are expected to be more significant improvements at 7nm than at any previous node, so rather th... » read more

Extending EUV Beyond 3nm

By Ed Sperling - 18 May, 2017 - Comments: 10

Jan van Schoot, senior principal architect at [getentity id="22935" comment="ASML"], sat down with Semiconductor Engineering to talk about how far EUV can be extended and where it is today. What follows are excerpts of that discussion. SE: High numerical aperture [gettech id="31045" comment="EUV"] has been in the works for some time as a way of extending EUV. How is this technology shaping... » read more

Inside Lithography And Masks

By Mark LaPedus - 05 Apr, 2017 - Comments: 3

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at [getentity id="22217" e_name="Imec"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; David Fried, chief technology officer at [getentity id="22210" e_name="Cove... » read more

Patterning Problems Pile Up

By Mark LaPedus - 20 Mar, 2017 - Comments: 4

Chipmakers are ramping up 16nm/14nm finFET processes, with 10nm and 7nm now moving into early production. But at 10nm and beyond, chipmakers are running into a new set of problems. While shrinking feature sizes of a device down to 10nm, 7nm, 5nm and perhaps beyond is possible using current and future fab equipment, there doesn't seem to be a simple way to solve the edge placement error (EPE)... » read more

Fractilia: Pattern Roughness Metrology

By Mark LaPedus - 21 Feb, 2017 - Comments: 1

A new startup has emerged and unveiled a technology that addresses one of the bigger but less understood problems in advanced lithography--pattern roughness. The startup, called Fractilia, is a software-based metrology tool that analyzes the CD-SEM images of pattern roughness on a wafer. Fractilia, a self-funded startup, is led by Chris Mack and Ed Charrier. Mack, known as the gentleman sc... » read more

Multi-Patterning Issues At 7nm, 5nm

By Ed Sperling - 28 Nov, 2016 - Comments: 13

Continuing to rely on 193nm immersion lithography with multiple patterning is becoming much more difficult at 7nm and 5nm. With the help of various resolution enhancement techniques, optical lithography using a deep ultraviolet excimer laser has been the workhorse patterning technology in the fab since the early 1980s. It is so closely tied with the continuation of [getkc id="74" comment="Mo... » read more

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tag: line-edge roughness