Research Bits: Oct. 29


Micro-LED DUV maskless lithography Researchers from the University of Science and Technology of China, Anhui GaN Semiconductor, and Wuhan University developed a vertically integrated micro-LED array for deep ultraviolet (DUV) maskless photolithography. The team fabricated a DUV display integrated chip with 564 pixels-per-inch density that uses a three-dimensional vertically integrated devic... » read more

Tuning Design And Process For High-NA EUV Stitching


By Kevin Lucas and James Ban Upcoming 14A and 10A process nodes will use high-NA EUV anamorphic scanners, which will require two stitched half-fields to achieve the equivalent wafer exposure area of previous-generation scanners, see figure 1. The lithography patterning at a stitching boundary between two mask exposures will be affected by additional process variation than are encountered in ... » read more

Luminary Panel Sees Multi-Beam Mask Writers And Curvilinear Masks Key To 193i And EUV


Attendance was up and the mood was optimistic at this year’s SPIE Photomask and EUV conference held September 29 through October 3, 2024. The optimism was apparent as well for multi-beam mask writers and curvilinear masks during the eBeam Initiative’s 15th annual reception and meeting held on October 1. In the eBeam Initiative’s annual Luminaries survey, 93% of those surveyed said that pu... » read more

High-NA EUV Lithography: Enhancing Resolution By Split Pupil Exposure (Fraunhofer, ASML)


A new technical paper titled "Resolution enhancement for high-numerical aperture extreme ultraviolet lithography by split pupil exposures: a modeling perspective" was published by researchers at Fraunhofer IISB and ASML. The open source paper published on SPIE states: "The lithographic imaging performance of extreme ultraviolet (EUV) lithography is limited by the efficiency of light diffrac... » read more

Block Copolymer and Sub-10nm Line Patterns By Directed Self-Assembly (Tokyo Tech)


A technical paper titled "Chemically tailored block copolymers for highly reliable sub-10-nm patterns by directed self-assembly" was published by researchers at Tokyo Institute of Technology and Tokyo Ohka Kogyo Co. Abstract "While block copolymer (BCP) lithography is theoretically capable of printing features smaller than 10 nm, developing practical BCPs for this purpose remains challeng... » read more

Research Bits: Aug. 20


EUV mirror interference lithography Researchers from the Paul Scherrer Institute developed an EUV lithography technique that can produce conductive tracks with a separation of just five nanometers by exposing the sample indirectly rather than directly. Called EUV mirror interference lithography (MIL), the technique uses two mutually coherent beams that are reflected onto the wafer by two id... » read more

Chip Industry Week In Review


The U.S. Department of Commerce and Texas Instruments (TI) signed a non-binding preliminary memorandum of terms to provide up to $1.6 billion in CHIPS Act funding towards TI’s investment of over $18 billion for three 300mm semiconductor wafer fabs under construction in Texas and Utah. TI also expects to get about $6 billion to $8 billion from the U.S. Department of Treasury’s Investmen... » read more

Classification and Localization of Semiconductor Defect Classes in Aggressive Pitches (imec, Screen)


A new technical paper titled "An Evaluation of Continual Learning for Advanced Node Semiconductor Defect Inspection" was published by Imec and SCREEN SPE Germany. Abstract "Deep learning-based semiconductor defect inspection has gained traction in recent years, offering a powerful and versatile approach that provides high accuracy, adaptability, and efficiency in detecting and classifying... » read more

Precision Patterning Options Emerge For Advanced Packaging


The chip industry is ratcheting up investments in advanced packaging as it strives to keep pace with demands for increased functionality and higher performance, including novel patterning technologies that can reduce costs and speed time to market. Success in advanced packages is partly dependent on effectively managing the interconnectivity between the chips, which requires increasingly pre... » read more

Metrology Analysis Tool For Photolithography Process Characterization At Advanced Nodes


Continued scaling of integrated circuits to smaller dimensions is still a viable way to increase compute power, achieve higher memory cell density, or reduce power consumption. These days, chip makers are using single-digit nanometer figures or even Angstrom to label their manufacturing technology nodes, which are associated with the size of features patterned during the lithography process. ... » read more

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