Making Sense Of DRAM

By Ed Sperling - 13 Dec, 2018 - Comments: 0

Graham Allan, senior manager for product marketing at Synopsys, examines the different types of DRAM, from GDDR to HBM, which markets they’re used in, and why there is such disparity between them. https://youtu.be/ynvcPfD2cZU __________________________________ See more tech talk videos here. » read more

Week In Review: Design, Low Power

By Jesse Allen - 07 Dec, 2018 - Comments: 0

RISC-V Western Digital announced big plans for RISC-V with a new open source RISC-V core, an open standard initiative for cache coherent memory over a network, and an open source RISC-V instruction set simulator. The SweRV Core features a 2-way superscalar design with a 32-bit, 9 stage pipeline core. It has clock speeds of up to 1.8Ghz on a 28mm CMOS process technology and will be used in vari... » read more

Week In Review: Design, Low Power

By Jesse Allen - 30 Nov, 2018 - Comments: 0

Tools & IP UltraSoC debuted functional safety-focused Lockstep Monitor, a set of configurable IP blocks that are protocol aware and can be used to cross-check outputs, bus transactions, code execution, and register states between two or more redundant systems. It supports all common lockstep / redundancy architectures, including full dual-redundant lockstep, split/lock, master/checker, and... » read more

Looking Beyond The CPU

By Brian Bailey - 29 Nov, 2018 - Comments: 0

CPUs no longer deliver the same kind of of performance improvements as in the past, raising questions across the industry about what comes next. The growth in processing power delivered by a single CPU core began stalling out at the beginning of the decade, when power-related issues such as heat and noise forced processor companies to add more cores rather than pushing up the clock frequency... » read more

Process Corner Explosion

By Ann Mutschler - 13 Sep, 2018 - Comments: 1

The number of corners that need to be checked is exploding at 7nm and below, fueled by everything from temperature and voltage to changes in metal. Lowering risk and increasing predictability of an SoC at those nodes starts with understanding what will happen when a design is manufactured on a particular foundry process, captured in process corners. This is basically a way of modeling what i... » read more

UPF-Aware Clock-Domain Crossing

By Ed Sperling - 29 Aug, 2018 - Comments: 0

Synopsys’ Namit Gupta talks with Semiconductor Engineering about low-power design techniques at the most advanced process nodes, including how to verify the impact of CDC on power at the register transfer level, how to avoid bugs caused by the post-RTL insertion of low-power devices such as isolation, retention and level shifters. https://youtu.be/HwRe9DHLfmg » read more

Baum: Finding SoC Power Flaws

By Kevin Fogarty - 28 Aug, 2018 - Comments: 0

A South Korean startup founded by a Samsung engineer-turned-researcher has created a tool that finds power design flaws early in the SoC design process. The startup, Baum, Inc., launched the second version of its power-modeling solution in June at DAC. The product is a power design-verification tool that uses high-level models to create analyses designed to spot design flaws that could creat... » read more

The Rising Cost Of 5G

By Ed Sperling - 22 Aug, 2018 - Comments: 0

Semiconductor Engineering sat down to talk about challenges and progress in 5G with Yorgos Koutsoyannopoulos, president and CEO of Helic; Mike Fitton, senior director of strategic planning and business development at Achronix; Sarah Yost, senior product marketing manager at National Instruments; and Arvind Vel, director of product management at ANSYS. What follows are excerpts of that conversat... » read more

Where FD-SOI Works Best (Part 2)

By Ed Sperling - 15 Aug, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss changes in the FD-SOI world and what's behind them, with James Lamb, deputy CTO for advanced semiconductor manufacturing and corporate technical fellow at Brewer Science; Giorgio Cesana, director of technical marketing at STMicroelectronics; Olivier Vatel, senior vice president and CTO at Screen Semiconductor Solutions; and Carlos Mazure, CTO at Soi... » read more

More Performance At The Edge

By Ed Sperling - 09 Aug, 2018 - Comments: 0

Shrinking features has been a relatively inexpensive way to improve performance and, at least for the past few decades, to lower power. While device scaling will continue all the way to 3nm and maybe even further, it will happen at a slower pace. Alongside of that scaling, though, there are different approaches on tap to ratchet up performance even with chips developed at older nodes. This i... » read more

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tag: low-power design

Making Sense Of DRAM

Week In Review: Design, Low Power

Week In Review: Design, Low Power

Looking Beyond The CPU

Process Corner Explosion

UPF-Aware Clock-Domain Crossing

Baum: Finding SoC Power Flaws

The Rising Cost Of 5G

Where FD-SOI Works Best (Part 2)

More Performance At The Edge

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