tag: low-power design

Why Inductance Is Good for Area, Power and Performance
By Magdy Abadir - 12 Mar, 2018 - Comments: 0

By Magdy Abadir and Yehea Ismail For chips designed at advanced technology nodes, interconnect is the dominant contributor towards delay, power consumption, and reliability. Major interconnects such as clock trees, power distribution networks and wide buses play a significant role in chip failure mechanisms such as jitter, noise coupling, power distribution droops, and electro-migration. ... » read more

Exponentials At The Edge
By Ed Sperling - 08 Mar, 2018 - Comments: 0

The age of portable communication has set off a scramble for devices that can achieve almost anything a desktop computer could handle even five years ago. But this is just the beginning. The big breakthrough with mobile devices was the ability to combine voice calls, text and eventually e-mail, providing the rudiments of a mobile office-all on a single charge of a battery that was light enou... » read more

IP And Power
By Brian Bailey - 08 Mar, 2018 - Comments: 0

[getkc id="108" kc_name="Power"] is quickly becoming a major differentiator for products, regardless of whether they are connected to a wall outlet or dependent on a battery. At the same time, increasing amounts of a chips content comes from third-party [getkc id="43" kc_name="IP"]. So how do system designers ensure that the complete system has an optimal power profile, and what can they do to ... » read more

FD-SOI Adoption Expands
By Ed Sperling - 21 Feb, 2018 - Comments: 2

Fully depleted silicon-on-insulator (FD-SOI) is gaining ground across a number of new markets, ranging from IoT to automotive to machine learning, and diverging sharply from its original position as a less costly alternative to finFET-based designs. For years, [getkc id="220" kc_name="FD-SOI"] has been viewed as an either/or solution targeted at the same markets as bulk [gettech id="31093" c... » read more

Customizing Power And Performance
By Ed Sperling - 08 Feb, 2018 - Comments: 0

Designing chips is getting more difficult, and not just for the obvious technical reasons. The bigger issue revolves around what these chips going to be used for-and how will they be used, both by the end user and in the context of other electronics. This was a pretty simple decision when hardware was developed somewhat independently of software, such as in the PC era. Technology generally d... » read more

Bridging Machine Learning’s Divide
By Brian Bailey - 08 Feb, 2018 - Comments: 0

There is a growing divide between those researching [getkc id="305" comment="machine learning"] (ML) in the cloud and those trying to perform inferencing using limited resources and power budgets. Researchers are using the most cost-effective hardware available to them, which happens to be GPUs filled with floating point arithmetic units. But this is an untenable solution for embedded infere... » read more

Pushing Performance Limits
By Brian Bailey - 08 Feb, 2018 - Comments: 0

Trying to squeeze the last bit of performance out of a chip sounds like a good idea, but it increases risk and cost, extends development time, reduced yield, and it may even limit the environments in which the chip can operate. And yet, given the amount of margin added at every step of the development process, it seems obvious that plenty of improvements could be made. "Every design can be o... » read more

Tech Talk: 7nm Process Variation
By Ed Sperling - 17 Jan, 2018 - Comments: 0

Ankur Gupta, director of field applications at ANSYS, discusses process variation and the problems it can cause at 10/7nm and beyond. https://youtu.be/WHNjFr1Da6s » read more

PowerDown: Power Efficiency
By Kevin Fogarty - 15 Jan, 2018 - Comments: 0

Power Down Semiconductor wants to make the batteries in smartphones and IoT devices last 10 times longer by not wasting power they’ve already used. Every time an intelligent device has a thought, it pulls power from a battery and sends it through its maze of wires and millions of gates to create a O or a 1 at key points in the control and logic circuits. “Think about how much energy... » read more

Turning Down The Power
By Jeff Dorsch - 11 Jan, 2018 - Comments: 0

Chip and system designers are giving greater weight to power issues these days. But will they inevitably hit a wall in accounting for ultra-low-power considerations? Performance, power, and area are the traditional attributes in chip design. Area was originally the main priority, with feature sizes constantly shrinking according to Moore's Law. Performance was in the saddle for many years. M... » read more

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