tag: low-power design

Using PCI Express L1 Sub-states To Minimize Power Consumption In Advanced Process Nodes
By Rita Horner - 10 Jul, 2014 - Comments: 0

The major sources of Internet traffic are shifting from wired to wireless and mobile devices. With the growing regulatory requirements and increased consumer pressure for more power-efficient products, designers need to better understand and optimize the power consumption of battery-operated devices. Power consumption of a portable device widely varies based on the user’s behavior and appl... » read more

Power IS Top Priority, Isn’t It?
By Ann Mutschler - 12 Jun, 2014 - Comments: 0

While I don’t mean to start a battle – or maybe I do! – I heard something last week during DAC that gave me pause. The person I was speaking with – who told me they ‘got in a little bit of trouble’ for saying this – reminded me of an interesting subject we had talked about previously, namely, that they did not believe power is the number one concern of engineering teams today. Ye... » read more

User Case Study: Using Formal To Verify Low Power Functionality And Eliminate Unwanted ‘Xs’
By Joseph Hupcey III - 10 Apr, 2014 - Comments: 3

The cynics among us might argue that the addition of low power circuitry is a clever scheme by the energy industry to cause an equal amount of power to be consumed by low power verification as is saved by end-user usage.  As if modern SoC verification wasn’t challenging enough, the addition of low power can create corner cases that can escape even the most well-written UVM testbenches.  Ind... » read more

With Low-Power Comes Great Responsibility
By Qazi Faheem Ahmed - 14 Feb, 2014 - Comments: 0

Recent trends in the consumer electronics market show a demand for short, slim, and light-weight but powerful devices (with the only exception being displays, which are getting larger). Therefore area, timing, and power have all become “critical” to design; whereas in the past, one was prioritized over the others depending on design requirements. However, power is the dominant factor tod... » read more

How To Achieve 10X Faster Power Integrity Analysis And Signoff
By Various Writers - 04 Dec, 2013 - Comments: 0

In our mobile computing era, system-on-chip (SoC) design has become much more complex, with challenges from complex design rules on advanced process nodes, low-power circuitry design techniques, and increasing circuit sizes. Power integrity is a crucial part of successful design signoff. This paper discusses a new tool that speeds power integrity analysis and signoff by 10X compared to other te... » read more

Lessons From The Big Apple
By John Ellis - 24 Oct, 2013 - Comments: 0

Apple this week announced some big changes in their product lineup. Having already released their MacBook Air with the power-sipping Intel Haswell processor, Apple has made further strides with an operating system upgrade that extends battery life by yet another 10% to 15%. For those deep into technology, you may already know that low-power design capability wasn’t created overnight. It h... » read more

Where’s The Juice?
By Ed Sperling - 18 Oct, 2013 - Comments: 0

Driving to work in an electric car is cool. Finding an available plug these days is not. A year ago, before the surge (no pun intended) in electric vehicle popularity, it used to be relatively easy to find a parking spot and a plug at most high-tech companies. In fact, sometimes it was the only available spot. In recent months that’s changed. It’s getting harder and much more stressful. ... » read more

Power Optimization Requires Higher-Level Thinking
By Ann Mutschler - 12 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler With consumer demand—much of it for power sensitive mobile devices—driving the bulk of semiconductor design activity, it would seem obvious that the way chips are designed would have changed to reflect that. But have they? From an EDA perspective, the term ‘system level’ is used to mean ‘product level’ but this may not be enough, especially when it come... » read more

How Secure Are Low-Power Techniques?
By Ann Mutschler - 12 Sep, 2013 - Comments: 0

As a chip designer, you and your team have done the best job possible to optimize power in your SoC, likely utilizing all of the low power techniques at your disposal. The chip tapes out, gets implemented into systems and it’s a success! Then the call comes that your chip has been hacked within the system it’s in and you and your team are left shaking your heads in wonder. I can imagine ... » read more

Power Optimization Requires Higher-Level Thinking
By Ann Mutschler - 12 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler With consumer demand—much of it for power sensitive mobile devices—driving the bulk of semiconductor design activity, it would seem obvious that the way chips are designed would have changed to reflect that. But have they? From an EDA perspective, the term ‘system level’ is used to mean ‘product level’ but this may not be enough, especially when it come... » read more

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