tag: low-power design

Low Power Drives Performance And TCO
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Pallab Chatterjee A common theme at this year’s Custom Integrated Circuit Conference was the reduction of power and power management while increasing data throughput. Historically, the show has featured new techniques for ultra high accuracy and brute force improvements in performance at all costs. The main theme this year was that in a world of mobile endpoint devices, the goal is to get... » read more

Hierarchical LP Design 2
By Luke Lang - 11 Aug, 2011 - Comments: 0

By Luke Lang Last month, I discussed two key features of the Common Power Format (CPF) that support hierarchical design methodology: boundary port and macro model. These are commands that need to be written to describe the power intent and drive the tools. Without these commands, it is extremely difficult to do hierarchical design. But with these commands, hierarchical power intent files are n... » read more

Extending Battery Life
By Ed Sperling - 21 Jul, 2011 - Comments: 0

By Ed Sperling In the past it was all about clock frequency. People bought the latest computer and frequently paid a premium because it could crunch numbers faster. But as computing moves from the desktop into handheld devices, that focus is radically changing. Low-Power Engineering caught up with Mark Bohr, senior fellow and director of Intel’s process architecture and integration, to ta... » read more

Applications And Low Power
By Ed Sperling - 12 May, 2011 - Comments: 0

By Pallab Chatterjee As new process technologies are being developed to make devices smaller, they are also driving the operating power lower for the devices and systems. The goal is to reduce the power requirements for the system and hence increase the functional life on a single battery charge. This concept has worked in the semiconductor industry from 10-micron processes down to the 6... » read more

Changes Ahead In Low-Power Design
By Ed Sperling - 25 Mar, 2011 - Comments: 0

One of the interesting things about low-power designs in ICs is just how effectively power-saving techniques are being designed into chips these days. At most of the larger chipmakers, and even at an increasing number of midsize fabless companies, the concepts for implementing low-power techniques are well understood, well tested and thoroughly familiar. Two years ago, when the mainstream of... » read more

Silence Is Golden
By Ann Mutschler - 01 Dec, 2010 - Comments: 0

As the industry continues to march along building devices with ever-increasing battery life, it is necessary to migrate to the latest and greatest process nodes, which as we all know are smaller and use lower voltages. However, any noise in the system—whether it was there before or you start to use something like USB 3.0 or SATA or something else—is actually going to increase the number of ... » read more

A New Reference For Low-Power Processors
By Ed Sperling - 09 Sep, 2010 - Comments: 0

By Pallab Chattejee Just how much power can you squeeze out of a processor without destroying performance? Ask IBM. The company introduced a new methodology for power and energy management on its multicore processor chips. The new PowerPC chip, the Power 7, has eight main processor cores each with its own L2 and L3 cache and two central memory controllers. The architecture for the design is... » read more

Estimating Power From Mobile Device Apps
By Ann Mutschler - 09 Sep, 2010 - Comments: 0

By Ann Steffora Mutschler How do software application developers – even the ones sitting at home on their living room sofas with laptops – measure the power consumption of their application on the target device? This is a big problem today (something that is painfully obvious to owners of iPhones or Blackberries), and it will only get bigger. Software engineers may think it is not their... » read more

Burn, Baby, Burn
By Ann Mutschler - 09 Sep, 2010 - Comments: 0

Obviously, software burns power on mobile devices, but exactly how? I found out recently, thanks to Pete Hardee, director of solutions marketing at Cadence Design Systems. Essentially, Hardee said, there are four ways that software burns power, following in order from most to least. First, depending on the mode, various peripherals are on and off and the big one for a smartphone is the LC... » read more

Giant Steps—Backward
By Ann Mutschler - 10 Jun, 2010 - Comments: 0

With DAC headlining next week, power is sure to take center stage given its prominence as a key pain point for design engineers that are always on the lookout for a new technique to ease their power management burdens. In many low-power designs, asynchronous technology may be just the thing. One of the biggest disadvantages of the clockless CPU is that most design tools assume a clocked CPU ... » read more

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