tag: low power

Tech Talk: Near-Threshold Power
By Ed Sperling - 13 Nov, 2017 - Comments: 2

Lauri Koskinen, CTO and founder of Minima Processor, and Ron Moore, vice president of marketing at ARM, talk about near-threshold computing, dynamic power and margining, and how these techniques can extend battery life and reduce energy consumption. https://youtu.be/BhiNFe4NYQU » read more

Lots Of Little Knobs For Power
By Ann Mutschler - 09 Nov, 2017 - Comments: 3

Dynamic power is becoming a much bigger worry at new nodes as more finFETs are packed on a die and wires shrink to the point where resistance and capacitance become first-order effects. Chipmakers began seeing dynamic power density issues with the first generation of [getkc id="185" kc_name="finFETs"]. While the 3D transistor structures reduced leakage current by providing better gate contro... » read more

Tech Talk: eFPGA LUTs
By Ed Sperling - 02 Nov, 2017 - Comments: 0

Cheng Wang, Flex Logix's senior vice president of engineering, explains how to use lookup tables in embedded FPGAs and which number of inputs is best for which application. https://youtu.be/ScnIbCOLcP4 » read more

Body Bias: What It Is, And Why You Should Care
By Flint Yoder - 12 Oct, 2017 - Comments: 1

In case you hadn’t noticed, the use of integrated circuits (ICs) has exploded over the past decade. From the cheapest novelty toy to automobiles to implanted medical devices, it seems like everything we touch has an electronic component in it somewhere. Not surprisingly, that growth has brought with it a vastly expanded number and variety of IC design requirements that design companies must s... » read more

Automated Body Bias Validation For High Performance, Low Power Electronics
By Mentor, a Siemens Business - 11 Oct, 2017 - Comments: 0

Using a device’s body bias effect allows designers to tune a circuit’s behavior to meet both power and performance specifications, but getting it right isn’t always easy. Accurate, fast, automated body bias verification is critical to ensure today’s complex designs meet demanding performance, reliability, and power usage specifications. To read more, click here. » read more

Synthesis Of Energy-Efficient FSMs Implemented In PLD Circuits
By Aldec - 27 Sep, 2017 - Comments: 0

The paper presents an outline of a simple synthesis method of energy-efficient FSMs. The idea consists in using local clock gating to selectively block the clock signal, if no transition of a state of a memory element is required. The research was dedicated to logic circuits using Programmable Logic Devices as the implementation platform, but the conclusions can be applied to any synchronous ci... » read more

Tech Talk: 7nm Thermal Effects
By Ed Sperling - 14 Sep, 2017 - Comments: 0

ANSYS' Karthik Srinivasan talks about the effect of heat on reliability at advanced process nodes, including self-heating, circuit aging, and how that will affect automotive electronics. https://youtu.be/SS6iAXp0Kn8   Related Tech Talk: 7nm Power Dealing with thermal effects, electromigration and other issues at the most advanced nodes. » read more

What Does “Low Power Optimization” Mean To You?
By Dave Pursley - 08 Jun, 2017 - Comments: 0

As I was researching some new low power capabilities, I asked this question of nearly every designer I met: “How important is low power optimization?” It turns out that it’s a pretty useless question because of course it’s important to just about everyone. After all, reducing power improves reliability and reduces design costs. And for chips destined for certain applications, such as mo... » read more

Tech Talk: Neural Networks
By Ed Sperling - 08 Jun, 2017 - Comments: 0

Megha Daga, senior technical marketing manager at Cadence, talks with Semiconductor Engineering about convolutional neural networks, including the bandwidth and compute challenges associated with them. » read more

Power Challenges At 10nm And Below
By Ann Mutschler - 11 May, 2017 - Comments: 1

Current density is becoming much more problematic at 10nm and beyond, increasing the amount of power management that needs to be incorporated into each chip and boosting both design costs and time to market. Current per unit of area has been rising since 90nm, forcing design teams to leverage a number of power-related strategies such as [getkc id="143" kc_name="dynamic voltage and frequency... » read more

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