tag: low power

Performance-IP: Less Memory Latency
By Ed Sperling - 02 May, 2017 - Comments: 0

The combination of more functionality on chips plus more contention for memories is forcing companies to look at different ways to improve performance. Just adding more processing power doesn't guarantee improved performance, and throwing more memory at a problem—either SRAM or multiple levels of cache—is expensive and not always faster. There are too many processors and too many request... » read more

Cloud Computing Chips Changing
By Ann Mutschler - 19 Apr, 2017 - Comments: 1

An explosion in cloud services is making chip design for the server market more challenging, more diverse, and much more competitive. Unlike datacenter number crunching of the past, the cloud addresses a broad range of applications and data types. So while a server chip architecture may work well for one application, it may not be the optimal choice for another. And the more those tasks beco... » read more

Power Management Validation
By Mentor, a Siemens Business - 08 Mar, 2017 - Comments: 0

Power consumption is becoming a critical aspect of hardware design. No longer is verifying an SoC solely answering the question “does it work?” Now designers must also answer the question “does it meet my power budget?” When trying to find power issues it is critical to run the complete system in a realistic manner—at the system-level when the design/verification team is looking at th... » read more

Fix Processes, Then Silos
By Ed Sperling - 09 Feb, 2017 - Comments: 0

Jack Welch, former CEO of GE, was a big proponent of what he called a "boundaryless corporation." It was a good sound bite, but it pales in comparison to former Intel CEO Andy Grove's philosophy of working out of a cubicle, just like the rest of his staff. While it's great to have corporate buy-in for breaking down silos, which are vertically integrated, the real problem for semiconductor c... » read more

Routing Signals At 7nm
By Ed Sperling - 09 Feb, 2017 - Comments: 0

[getperson id="11763" comment="Tobias Bjerregaard"], [getentity id="22908" e_name="Teklatech's"] CEO, discusses the challenges of designs at 7nm and beyond, including power integrity, how to reduce IR drop and timing issues, and how to improve the economics of scaling. SE: How much further can device scaling go? Bjerregaard: The way you should look at this is [getkc id="74" comment="Moore... » read more

The Fundamental Power States For UPF Modeling And Power Aware Verification
By Mentor, a Siemens Business - 11 Jan, 2017 - Comments: 0

The IEEE 1801-2015 specifies the new semantics of power states through the ‘add_power_state’ UPF command. This new construct primarily allows incremental refinement of power states for power domains and its associated supply sets. The refinement concepts are actually originated from the fundamental conceptual set of power states termed as indefinite, definite, and deferred power states. In ... » read more

Tech Talk: Extending DRAM
By Ed Sperling - 09 Jan, 2017 - Comments: 0

Bruce Bateman, senior principal engineer at Kilopass, talks about how to extend the life of DRAM and how to work with smaller, denser memory.   Related Stories Executive Insight: Charlie Cheng Kilopass’ CEO talks about how to cut the capacitor in DRAM and why that’s important in the data center. » read more

Verification Of Low-Power Designs With Portable Stimulus
By Tom Anderson - 08 Dec, 2016 - Comments: 0

In a recent blog post, Steve Carlson talked about the use of software-driven tests to support concurrent power and performance analysis. Generation of software-driven tests is one of the key technologies that will be enabled by the upcoming standard from Accellera's Portable Stimulus Working Group (PSWG). Portable stimulus spans functional verification as well as performance validation, so PSWG... » read more

7nm Power Issues And Solutions
By Preeti Gupta - 16 Nov, 2016 - Comments: 0

Being able to achieve 35% speed improvement, 65% power reduction and 3.3X higher density makes adopting a 7nm process for your next system-on-chip (SoC) design seem like an easy decision. However, with $271 million in estimated total design cost and 500 man-years it would take to bring a mid-range 7nm SoC to production, companies need to carefully weigh the benefits against the cost of designin... » read more

The Time Dimension Of Power
By Brian Bailey - 10 Nov, 2016 - Comments: 0

Power is the flow of energy over time. While both aspects of that equation are important, they are important to different people in different ways. Energy that moves too quickly can cause significant damage. Too much energy moving over time can mean a non-competitive product, from battery-powered devices to a wide array of locations such as the datacenter. When the industry talks about power... » read more

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