Debug This! How To Simplify Coverage Analysis And Closure

By Yara Essam - 10 Oct, 2022 - Comments: 0

For years the process of ASIC and FPGA design and verification debug consisted primarily of comprehending the structure and source code of the design with waveforms showing activity over time, based on testbench stimulus. Today, functional verification is exponentially complex with the emergence of new layers of design requirements (beyond basic functionality) that did not exist years ago — f... » read more

Low Power HW Accelerator for FP16 Matrix Multiplications For Tight Integration Within RISC-V Cores

By Technical Paper Link - 03 Aug, 2022 - Comments: 0

This new technical paper titled "RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs" was published by researchers at University of Bologna and ETH Zurich. According to their abstract: "One of the key stumbling stones is the need for parallel floating-point operations, which are considered unaffordable on sub-100 mW extre... » read more

Edge-AI Hardware for Extended Reality

By Technical Paper Link - 20 Jul, 2022 - Comments: 0

New technical paper titled "Memory-Oriented Design-Space Exploration of Edge-AI Hardware for XR Applications" from researchers at Indian Institute of Technology Delhi and Reality Labs Research, Meta. Abstract "Low-Power Edge-AI capabilities are essential for on-device extended reality (XR) applications to support the vision of Metaverse. In this work, we investigate two representative XR w... » read more

There Is Plenty Of Room At The Top: Imagining Miniaturized Electro-Mechanical Switches In Low-Power Computing Applications

By Gerold Schröpfer - 19 May, 2022 - Comments: 0

The first computers were built using electro-mechanical components, unlike today’s modern electronic systems. Alan Turing’s cryptanalysis multiplier and Konrad Zuse’s Z2 were invented and built in the first half of the 20th century, and were among the first computers ever constructed. Electro-mechanical switches and relays performed logic operations in these machines. Even after computers... » read more

Image Sensor Trained To Classify Optically Projected Images By Reading Out The Few Most Relevant Pixels

By Technical Paper Link - 30 Apr, 2022 - Comments: 0

New research paper "Sparse pixel image sensor" from Institute of Photonics, Vienna University of Technology. Abstract "As conventional frame-based cameras suffer from high energy consumption and latency, several new types of image sensors have been devised, with some of them exploiting the sparsity of natural images in some transform domain. Instead of sampling the full image, those devices... » read more

Architecting Faster Computers

By Brian Bailey - 14 Apr, 2022 - Comments: 3

To create faster computers, the industry must take a major step back and re-examine choices that were made half a century ago. One of the most likely approaches involves dropping demands for determinism, and this is being attempted in several different forms. Since the establishment of the von Neumann architecture for computers, small, incremental improvements have been made to architectures... » read more

Brokerage System for Integration of LrWPAN Technologies

By Technical Paper Link - 01 Apr, 2022 - Comments: 0

New academic paper from UK's Leeds Beckett University. Abstract "The prevalent demand for remote data sharing and connectivity has catalysed the development of many wireless network technologies. However, low-power and low-rate wireless network technologies have emerged as the preferred choice (due to cheap procurement and maintenance cost, efficiency, and adaptability). Currently, these gr... » read more

A Framework For Ultra Low-Power Hardware Accelerators Using NNs For Embedded Time Series Classification

By Fraunhofer IIS/EAS - 09 Mar, 2022 - Comments: 0

In embedded applications that use neural networks (NNs) for classification tasks, it is important to not only minimize the power consumption of the NN calculation, but of the whole system. Optimization approaches for individual parts exist, such as quantization of the NN or analog calculation of arithmetic operations. However, there is no holistic approach for a complete embedded system design ... » read more

A Low-Power BLS12-381 Pairing Cryptoprocessor for Internet-of-Things Security Applications

By Technical Paper Link - 21 Feb, 2022 - Comments: 0

Abstract: "We present the first BLS12-381 elliptic-curve pairing cryptoprocessor for Internet-of-Things (IoT) security applications. Efficient finite-field arithmetic and algorithm-architecture co-optimizations together enable two orders of magnitude energy savings. We implement several countermeasures against timing and power side-channel attacks. Our cryptoprocessor is programmable to provid... » read more

An Event-Driven and Fully Synthesizable Architecture for Spiking Neural Networks

By Technical Paper Link - 20 Dec, 2021 - Comments: 0

Abstract: "The development of brain-inspired neuromorphic computing architectures as a paradigm for Artificial Intelligence (AI) at the edge is a candidate solution that can meet strict energy and cost reduction constraints in the Internet of Things (IoT) application areas. Toward this goal, we present μBrain: the first digital yet fully event-driven without clock architecture, with co-lo... » read more

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Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: low power