tag: low voltage

How Low Can You Go? Pushing The Limits Of Transistors
By Synopsys - 08 Mar, 2023 - Comments: 0

Deep low voltage enablement of embedded memories and logic libraries to achieve extreme low power: Rising demand for cutting-edge mobile, IoT, and wearable devices, along with high compute demands for AI and 5G/6G communications, has driven the need for lower power systems-on-chip (SoCs). This is not only a concern for a device’s power consumption when active (dynamic power), but also when... » read more

Wearable Electrotactile Rendering System w/High Spacial resolution, Rapid Refresh
By Technical Paper Link - 24 Oct, 2022 - Comments: 0

A new technical paper titled "Super-resolution wearable electrotactile rendering system" was published by researchers at City University of Hong Kong (CityU) and Tencent Technology's Robotics X Laboratory. "Here, we present a wearable electrotactile rendering system that elicits tactile stimuli with both high spatial resolution (76 dots/cm2) and rapid refresh rates (4 kHz), because of a prev... » read more

Designing and Simulating Low-Voltage CMOS Circuits Using Four-Parameter Model
By Technical Paper Link - 20 Jun, 2022 - Comments: 0

New technical paper titled "Bridging the Gap between Design and Simulation of Low-Voltage CMOS Circuits" from researchers at Federal University of Santa Catarina, Brazil. Abstract "This work proposes a truly compact MOSFET model that contains only four parameters to assist an integrated circuits (IC) designer in a design by hand. The four-parameter model (4PM) is based on the advanced com... » read more

Timing Is Of The Essence
By Ansys - 14 Mar, 2019 - Comments: 0

Today's advanced 16/7nm system-on-chips (SoCs) are faced with increased variation as they push for lower power. While the sizes of the transistors continue to shrink following Moore's Law, the threshold voltages fail to scale. This causes wide timing variability leading to timing closure difficulties, design re-spins and poor functional yield. Learn how ANSYS Path FX with its unique variatio... » read more

Tech Talk: Extending DRAM
By Ed Sperling - 09 Jan, 2017 - Comments: 0

Bruce Bateman, senior principal engineer at Kilopass, talks about how to extend the life of DRAM and how to work with smaller, denser memory.   Related Stories Executive Insight: Charlie Cheng Kilopass’ CEO talks about how to cut the capacitor in DRAM and why that’s important in the data center. » read more

Performance Plus Lower Power
By Ed Sperling - 06 Oct, 2011 - Comments: 0

A new race is beginning in the SoC world. While performance has been supplanted by battery life as the top goal for the next process node, that prioritization isn’t going to last. The ultimate challenge will be to achieve both—higher performance with substantially lower power. This is the subject of research inside of dozens of companies and universities, and there are several different... » read more

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