Is There Light At The End Of Moore’s Tunnel?

By Brian Bailey - 18 Dec, 2013 - Comments: 2

Last month’s article, “Is There Light At The End Of Moore’s Tunnel,” examined the state of the industry in terms of integrating photonics components onto silicon. It concentrated on the piece that has been the hardest to achieve – the laser. However, as realizing that integration goal has become closer to reality, it has also waned in terms of the number of people who believe it is th... » read more

Fixing DP Errors: Colors Or Rings

By Ann Mutschler - 18 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler With the move to the 20nm manufacturing node, double patterning (DP) became a requirement. In addition, topology changes occurred that demanded very regular structures, marking a significant departure from 28nm design. As a result of this new approach, new errors are popping up, such as DP violation loops, odd cycle violations and anchor path violations. Certain... » read more

Verifying Your Intent

By Ann Mutschler - 21 Mar, 2013 - Comments: 0

Design rule checking (DRC), layout versus schematic (LVS) and electrical rule checking (ERC) are physical verification techniques that are mandatory today to check a design and its structures before manufacturing. Checking electrical characteristics of a design is one thing. Verifying power intent is quite another. And the overlap of the two is an intriguing concept. Case in point: Checking fo... » read more

Newer posts →

Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: LVS

Is There Light At The End Of Moore’s Tunnel?

Fixing DP Errors: Colors Or Rings

Verifying Your Intent

Trending Articles

Hybrid Bonding Makes Strides Toward Manufacturability

Americas Chip Funding Energizes Industry

Advanced Packaging Driving New Collaboration Across Supply Chain

Chiplets Make Progress Using Interconnects As Glue

2D Semiconductors Make Progress, But So Does Silicon

Knowledge Centers
Entities, people and technologies explored