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You’re Not Alone


All too often we get caught up in our own work and our own issues, thinking no one else could possibly be having as much trouble as we are. The reality is that many, if not most, of the problems and challenges in IC verification are not unique to one design, one team, or one person. The natural reluctance of people to admit they are struggling with some aspect of their job often keeps them from... » read more

Is There Light At The End Of Moore’s Tunnel?


Last month’s article, “Is There Light At The End Of Moore’s Tunnel,” examined the state of the industry in terms of integrating photonics components onto silicon. It concentrated on the piece that has been the hardest to achieve – the laser. However, as realizing that integration goal has become closer to reality, it has also waned in terms of the number of people who believe it is th... » read more

Fixing DP Errors: Colors Or Rings


By Ann Steffora Mutschler With the move to the 20nm manufacturing node, double patterning (DP) became a requirement. In addition, topology changes occurred that demanded very regular structures, marking a significant departure from 28nm design. As a result of this new approach, new errors are popping up, such as DP violation loops, odd cycle violations and anchor path violations. Certain... » read more

Verifying Your Intent


Design rule checking (DRC), layout versus schematic (LVS) and electrical rule checking (ERC) are physical verification techniques that are mandatory today to check a design and its structures before manufacturing. Checking electrical characteristics of a design is one thing. Verifying power intent is quite another. And the overlap of the two is an intriguing concept. Case in point: Checking fo... » read more

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