A Reliability Baseline Is Essential For Today’s Complex IC Designs

Successful verification requires more than just DRC and LVS rule decks.


Design rule checking (DRC) represents a common platform by which we can all compare relative rule complexity. The industry expectation is that all foundries will provide complete DRC and layout vs. schematic (LVS) rule decks at all process nodes for the successful tape-out of IC designs. However, not only are DRC operations growing significantly (Figure 1), but the scope of the rules needed to ensure manufacturability and performance is expanding. Because the context of many checks (e.g., voltage-aware DRC, FinFET-specific DRC, and multi-patterning DRC) is now vitally important to the successful verification of chips, IC designers and verification teams are demanding much more than just DRC and LVS rule decks that ensure their design can be printed accurately and match the source netlist.

Figure 1: Growth in DRC rule check number and complexity.

With the plethora of process nodes and variants now available to design companies, multiple foundries are competing for new business, and have created compelling offerings to entice these companies to move the next design to their platform. While node migration is still a popular choice for scaling (and improving cost per transistor), many foundries are responding to their customers’ needs by introducing new process nodes at larger established nodes that are well-matched to the design complexity, power profile, and reliability needs of many design starts. This “upsizing” effort to create a complete and well-balanced portfolio [1][2][3] includes the necessary baseline rule decks (DRC, LVS), as well as design for manufacturing (DFM) and reliability rule decks needed to adequately verify and optimize these designs. The availability of a complete and robust reliability verification [4] environment is being sought after with greater frequency and need, and has become a greater factor in the choice of foundry.

Reliability verification
Today, designers, CAD departments, and reliability verification engineers are getting a helping hand from many foundries who offer reliability rule decks that leverage automated reliability verification. Such foundry rule decks create a baseline for reliability acceptance throughout the entire design flow, from IP to full-chip reliability applications. In addition, knowing how to apply the precise rules of a new process node is easier when a foundry-supported reliability rule deck is available [5]. Design companies with access to a foundry-supported reliability rule deck can be assured that complex reliability susceptibilities in their designs can be found, analyzed, and properly corrected during verification.

IP validation
Contributing a significant portion of today’s designs is intellectual property (IP) re-use. Whether it is IP developed internally from previous projects or sourced externally, a significant challenge for this re-use is the determination of suitability. While the physical layout of an IP block used in a previous design may remain unchanged, the context of how that IP block is used in a new design must be validated. Figure 2 shows well-trusted IP with multiple power domains, with unified power format (UPF) power state tables (PST). While the IP may work well in a standalone context, validation of how they interact with (and are physically connected within) the new IC design as a whole must be rigorously performed, particularly when validating interactions of multiple power domains.

Figure 2: Well-trusted IP with multiple power domains.

IP from multiple sources are likely to contain different design styles and techniques. While these often demonstrate the creativity of the designers, there are times where validation of consistent design styles and best practices provide a platform for simplified long-term maintenance and improved cost of ownership. Identifying these differences early in the design process helps eliminate late-breaking issues during IP integration and assembly. For example, one design decision in which consistency is valuable across teams is the choice of which common ESD techniques to use for IO pin protection.

Validation of IP becomes even harder when it also involves a process node or foundry change. Retargeting IP can be especially challenging when applying a process shrink, because special care must be taken with those parts of the design that should not shrink, such as interconnect robustness and device sizing for ESD protection. While shrinking interconnect, transistor dimensions, and spacings for most of the design may be appropriate for the new node, maintaining correct geometrical dimensions where energy needs to be shunted, as is the case for ESD protection circuitry, requires careful validation. While new nodes may offer new opportunities to improve device performance, they may also require different design considerations, such as a transition from planar bulk transistors to FinFET or FD-SOI. These considerations can be crucial when targeting power-sensitive applications like Internet of Things (IoT) applications, or effectively using body biasing [6][7] techniques.

Full-chip integration
The verification of individual IPs provides a foundation for tackling the verification of your chip assembly. However, standalone IP verification lacks the overall context of how these will be incorporated into the larger design. Comprehensive verification at the full-chip level is an equally important consideration. Rule decks used for both IP and full-chip runs often have settings or modes that are used to define the verification level to create the appropriate results. Overall chip context is an important aspect of validating critical reliability applications (Figure 3), including ESD, electrical overstress (EOS), voltage-aware DRC, and interconnect robustness checking (particularly critical for avoiding charge device model (CDM) issues by ensuring low resistance between ESD clamps).

Figure 3: Reliability applications necessary for thorough verification of critical reliability design issues.

While still applicable at the IP level, some reliability checks must also be performed in the context of the full chip. In the case of device-level EOS, long-term reliability issues will arise if the bulk is tied to a higher voltage than what the gate is switching at. This scenario creates a gate-oxide stress that will cause a failure over time. These types of failures are challenging to recognize, as they are subtle design errors not easily identified through traditional SPICE simulations (think input vectors to expose and waveform review necessary to detect, for all transistors and power modes). To ensure that time dependent dielectric breakdown (TDDB) does not lead to premature oxide breakdown of interconnect, spacing checks must be performed in a manner that considers the voltages on these interconnects. This checking technique is often referred to as voltage-aware DRC (VA-DRC).

While most designers expect basic ESD checking from their automated tool flows, more complex full-chip reliability checks like interconnect robustness verification with point-to-point (P2P) and current density (CD) analysis are critical. CDM checking to protect gates that are directly connected to power/ground are needed due to the shrinking of gate oxide thickness and concerns across power domains. When active clamps are used, there is a need to validate resistance between global powers (of different domains) to avoid CDM issues.

Custom checks
While foundry reliability rule decks provide baseline reliability checks, there may be occasions where, just like the foundry-provided DRC checks, verification teams or designers may choose to augment these checks based on the target industry and the expected customer use profile of their product. Of particular focus is verifying the reliability of analog device constraints [8], electrostatic discharge (ESD) paths and related interconnect [9][10][2][11], along with enhancements in the field of latch-up verification [12].

The foundry-provided ESD/latch-up rules are a great place to start for developing a reliability baseline, but depending on what your foundry provides, additions to your full-chip checklist might need to include:

  • Validation that all IPs are correctly implemented
  • Latch-up protection verification
  • Interconnect robustness analysis
  • Stacked devices analysis in the context of the whole chip
  • Verification that the correct power ties are used in wells

Industry adoption
Each foundry’s offerings have a different focus. ESD protection is the common thread amongst all, with diversity in other areas. For example, the Taiwan Semiconductor Manufacturing Company (TSMC) focuses on ESD, interconnect reliability, and latch-up [9][13][14], at both the IP and full-chip level. TSMC has been a leader in reliability verification, paving the way for other foundries to follow [15]. After creating the TSMC9000 IP quality program [16] for their customers to improve IP dependability, TSMC then extended the design rules to create a high-reliability ecosystem that included complete ESD/latch-up coverage. On supported nodes, all TSMC9000 IPs with a 100% score have been validated with the Calibre PERC reliability platform from Mentor, a Siemens Business [5].

TowerJazz, who already supported checks for power management, ESD and CDM protection as part of the TowerJazz PDK offering, announced their support for a new suite of analog design constraint checks, which include device alignment, symmetry, orientation/parameter matching, and more (Figure 4). These checks leverage both the delicate analog layout requirements and automotive reliability check templates available for use with the Calibre PERC reliability platform [8].

Figure 4: Subtle design errors are often difficult to identify without automated validation. [17]

The automotive reliability check templates were developed as an outcome of the German RESCAR 2.0 program, which is focused on increasing the robustness of electronic circuits in automotive environments. Member companies Infineon Technologies AG and Robert Bosch GmbH of this program selected the Calibre PERC platform as the electronic design automation (EDA) reliability platform, using the Calibre PERC-based automotive reliability check templates for the verification of essential robustness constraints [8].

TowerJazz is the first commercial foundry to incorporate these RESCAR-developed reliability checks into their standard design kit offering. These checks enable designers to address the enhanced level of reliability compliance that automotive industry standards, such as the international functional safety standard ISO 26262, are now requiring from the entire automotive supply chain. Even though these reliability checks are targeted at analog design, they can be used to analyze and enhance the reliability of any IC design [8].

In today’s demanding markets, both 3rd-party IP and internal IP should go through the same rigorous reliability verification before being introduced into the larger design. These checks often include not only reliability verification, but also validation of consistent design styles and best practices that lead to simplified maintenance and improved long-term cost of ownership.

Foundry-provided rule decks enable design companies to establish baseline robustness and reliability criteria. Automation of both reliability and design consistency checks replaces manual inspection, which is time-consuming and error prone, with an efficient, consistent, and repeatable reliability verification process. The ability to add customized checks to this baseline delivers complete coverage for both the foundry and internal reliability rule decks.

When transitioning to new process nodes, design companies must consider their entire ecosystem, from IP provider to final chip assembly, to ensure they have a consistent, complete, and accurate reliability verification solution. Without that verification, device performance and product life become uncertain promises in a demanding and often unforgiving market.


  1. Mentor Graphics Announces Collaboration with GLOBALFOUNDRIES on Reference Flow and Process Design Kit for 22FDX Platform, 9, 2015. Mentor Graphics Corporation. http://bit.ly/2o4NQYR
  2. Mentor Graphics Announces Further Certification of Mentor Software for TSMC 12FFC and 7 nm Processes, March 15, 2017. Mentor Graphics Corporation. http://bit.ly/2F1fs9n
  3. Intel Custom Foundry certifies Mentor physical verification tools for 22FFL FinFET low power process, 19, 2017. Mentor, a Siemens Business. http://bit.ly/2Ckcr0S
  4. Reliability Verification, June 6, 2016. Semiconductor Engineering. http://semiengineering.com/kc/knowledge_center/Reliability-Verification/244
  5. Mentor Graphics Calibre PERC Reliability Checking Solution Used for IP Quality Program by TSMC, 29, 2013. Mentor Graphics Corporation. http://bit.ly/2BYDLpB
  6. Yoder, Automated Body Bias Validation for High Performance, Low Power Electronics, Oct. 2017. Mentor, a Siemens Business. http://bit.ly/2F2pIhF
  7. Mutschler, Ann (Nov. 15, 2017). The Return of Body Semiconductor Engineering. https://semiengineering.com/the-return-of-body-biasing/
  8. Mentor and TowerJazz provide first commercial comprehensive suite of analog constraint checks for enhanced automotive reliability offering, 2, 2017. Mentor, a Siemens Business. http://bit.ly/2CiFYbc
  9. Mentor extends solutions to support TSMC 7nm FinFET Plus and 12nm FinFET process technologies, 13, 2017. Mentor, a Siemens Business. http://bit.ly/2sullsY
  10. Mentor Announces Availability of Tools and Flows for Samsung 8LPP and 7LPP Process Technologies, May 24, 2017. Mentor, a Siemens Business. http://bit.ly/2EoBoKt
  11. Mentor Graphics Announces Availability of Qualified Calibre PERC Rule Decks for UMC 28nm Technology, 19, 2016. Mentor Graphics Corporation. http://bit.ly/2nXQfVT
  12. Hogan, Matthew. Automated and Context-Aware Latch-Up Checking with the Calibre PERC Reliability Platform, June 2017. Mentor, a Siemens Business. http://bit.ly/2nYoywh
  13. Mentor extends solutions for TSMC InFO and CoWoS design flows to help customers continue IC innovations, Sept. 13, 2017. Mentor, a Siemens Business. http://bit.ly/2ED3FA7
  14. Mentor Graphics Design and Verification Tools Certified for TSMC 16nm FinFET Production, April 15, 2014. Mentor Graphics Corporation. http://bit.ly/2Ep9wd3
  15. Mentor Graphics Joins GLOBALFOUNDRIES FDXcelerator Partner Program, 22, 2016. Mentor Graphics Corporation. http://bit.ly/2o4NMZ7
  16. TSMC9000 Program, http://www.tsmc.com/english/dedicatedFoundry/services/tsmc9000.htm
  17. Bexten, et. al. Physical Verification Flow for Hierarchical Analog IC Design Constraints, January 2015, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7059047

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