The Return Of Body Biasing

This technique lets engineering teams reach new power lows, but it’s not always so simple.


Body biasing is making a comeback across a wide swath of process nodes as designers wrestle with how to build mobile devices with more functionality and longer battery life.

Consider an ultra-low-power IoT device with a wireless sensor, for example, which is meant to last for years without changing a battery. Body biasing can be used to create an ultra-low-leakage sleep state.

“In that world, you’d put the device in a state where the Vt was essentially as high as you could realistically make it without causing a whole realm of other things to happen if your operating voltage gets too close to your threshold voltage,” explained Arm fellow Rob Aitken. “It’s basically making the Vt high enough to shut off all the devices, and that would be worth it to you because in essentially all of these systems, the number one source of energy consumption is the sleep state. That dwarfs everything else. So if you make your sleep state 10X less power hungry, you have made your battery last pretty close to 10X longer.”

Body biasing is not new. In fact, this technique was used in the past even on bulk technologies. But after 40nm it loses its efficacy with bulk CMOS, which is why companies like GlobalFoundries and STMicroelectronics have swapped to FD-SOI.

“In 40nm (bulk) it was already limited,” said Giorgio Cesana, marketing director at STMicroelectronics. “At 28nm it was almost nothing. And in finFET, it doesn’t work. What is happening is that FD-SOI is bringing back the body bias, not only with a good effectiveness in terms of trimming of the Vt, but also in terms of the Vdd range that we can apply for the biasing, because in the bulk technologies we were limited at +/- 300 millivolt. With FD-SOI, we can go with a much larger range.”

Fig. 1: Body biasing is more efficient in FD-SOI because of the transistor construction and ultra-thin insulator layer. The buried oxide also allows for higher biasing voltages. Source: STMicroelectronics

What is body biasing?
Body biasing allows for a more intricate level of control of the threshold voltage in a design.

“For example, when you want to use ultra low voltage to 0.6 volt or even 0.5 volt power supply, the problem is that you arrive at a voltage that is very close to the threshold voltage of the transistor,” Cesana said. “The min-max effects that you have to guarantee with the Vdd mean that with slow-fast spread, with temperature min-max, you may discover that the low temperature/low voltage is really the worst case. While you take a transistor at 0.8 or 0.9 volt on the same process, for example, and you want a range of -40° and 125° C, you have a swing in temperature on the speed, which is moderate. Depending on voltage that can be 10% or 15%. But the min-max is not that different, so closing the timing is not that critical. When you’re at 0.5 volt, for example, with the same process corners between -40° and 125° C, the difference in timing is 3X. You can imagine signing off timing with such a large spread on the timings. It’s practically Mission Impossible. Or when you do this, you do a lot of over-design because you are obliged to sign off at -40, even though your device will never be at -40. It will already be at 0° or even higher. If now you can have a temperature sensor, or multiple temperature sensors, inside your chip and you have a body bias generator, you can, depending on the temperature, body bias the transistor and speed up the transistor by applying forward body bias when you are at a low temperature. When you apply forward body bias, you lower the threshold voltage, you speed up your transistor, you increase your leakage. But process compensation is not a problem because you want to speed up slow transistors that have low leakage. For temperature compensation, you have exactly the same problem. You want to speed up transistors that are at -40° C or 0° C. They are at low temperature so they are not leaking. So you can play the trick.”

There is always a tradeoff between performance and the amount of voltage needed to turn on circuits.

“A faster chip is faster because the transistors turn on at a lower threshold voltage,” said Drew Wingard, CTO of Sonics. “And because they turn on at a lower threshold voltage, that means they don’t turn off very well, or don’t turn off as well, so their leakage is by definition going to be much higher than slower chips. As a result, if you have to set up the infrastructure—especially the voltage levels so that the slow transistors work—that voltage is way too high for the fast transistors. The worst case energy dissipation and the worst case thermal conditions will be when you’ve got a fast chip that is running at a voltage that is too high, or higher than is needed.”

With techniques like dynamic voltage and frequency scaling, you can take advantage of fast chips and play with the voltage supply. “But that’s actually a bit more expensive than some people are willing to pay, because now you have to have programmable voltage regulators or power management ICs off chip that have tunable things,” Wingard said. “Another approach, especially with FD-SOI, is to use back bias/body bias/the invisible fourth terminal on those transistors to tune the threshold voltage so that you can make slow transistors faster and fast transistors slower. By doing that you can electrically reduce the transistor skew between different lots of wafers or different die on the same wafer. This is a much less expensive technique than DVFS, and can be used very effectively to essentially center the yield or increase the yield or reduce the energy.”

Verification considerations
Everything has a ripple effect, though, and modifying the threshold voltage can have an impact on the overall functionality of a device.

“We are looking to really understand the methodology being used,” said Flint Yoder, a technical marketing engineer at Mentor, a Siemens Business. “There may be a library of devices or cells that are expected to be under certain bias condition. We also need to understand, within the context of the design, the voltages and the various power domains and whether those are specifically for biasing. And we need to analyze the connectivity of those devices or those different libraries.”

The goal is to understand the biasing state of a current device and whether it matches the expectation for the process. In this case, a backend process will alter the performance characteristics of a design.

“This is why you frequently see chips out there today that will have different voltage operating levels, based on whether they are colloquially in a turbo mode or a normal mode,” said Stuart Clubb, a product marketing manager at Mentor. “The engineer now has more corners that he has to deal with because somebody is going to turn around and say, ‘The specs say that we need an 800 MHz normal mode, a 300 MHz low-power mode and a 1 GHz turbo mode. Make that work.’ From a pure timing analysis perspective, if the RTL designer is working a lot with DC RC generators, now he’s going to need to know if this is synthesized for the 1 GHz turbo. Is it going to meet my 800 MHz regular at the same voltage? And is it going to meet my very low power by messing around with the bias or the supply voltage or anything else? This introduces way more corners. You might get lucky and design it for the fastest performance and find that you’ve got to meet the 1 GHz. But with the normal 800 MHz, maybe there’s a bunch of positive slack there because you designed part of the design to be really good for that 1 GHz, but it was really generous for the 1 GHz. So that part of the design could have run at 1.2. However, as a designer I don’t see that because all I get is my worst critical path. I can’t look at every single register to register timing that I crafted.”

RTL engineers have a tendency to over-pipeline and over-engineer, because if the timing and functionality don’t meet the spec, they are dead in the water, Clubb said. “In most design processes, unless you are a company that has a philosophical mindset where every RTL designer owns power and everybody is measured on power and wasted power and analysis of where they are wasting power, power is usually the first victim of the late schedule.”

Using body biasing
There are multiple ways to do body biasing.

“There’s the permanent setting of it—choosing some value and setting it there, versus adaptive body biasing or dynamic body biasing of various sorts that attempts to get kind of a broadened spectrum between higher performance and lower power than you would get by fixing just a fixed spot,” Arm’s Aitken explained. “The point of body biasing is to change the threshold voltage, and changing the threshold voltage essentially changes the operating characteristic of the transistor. The lower the threshold voltage, the higher performance, but also the leakier it is. The higher the threshold voltage is the inverse.”

Designers also should keep in mind that with body biasing, the goal is to change the threshold voltage in a way that is more conducive to what you want to accomplish.

“If you want a lower-leakage system, then you essentially use the body biasing to effectively raise the threshold voltage,” Aitken said. “And if you want a higher-performance system, you use it to essentially lower the threshold voltage. With an adaptive scheme, you’re trying to do that on the fly in a way in that you might say, ‘I want to have a normal mode, and then I want to have a burst mode. In burst mode, I’m going to boost the frequency up, and the way I will enable that frequency boost is to essentially lower the Vt of all of the devices so they go faster. From a design standpoint, that’s a neat thing. The ability to have that knob and be able to change the design dynamically is really cool. But it’s not trivial to implement it.”

The first question to answer is what process is being targeted, Aitken said. “If you are using an FD-SOI type of process, then biasing the substrate is fairly straightforward because the insulator is just sitting there. There are some mechanics to doing it, but the process is tuned to do it easily. If you’re using conventional CMOS, then you need a triple well process in order to make sure that you have the ability to isolate both the n-wells and the p-wells, and bias them. So there’s an additional step necessary in a conventional CMOS device that isn’t necessary in FD-SOI. That’s only step one. The next step is, ‘Alright I’ve come up with this idea of I’m going to do a body bias. How do I do that? I have to have some power supply someplace that is connected to the body, and then is settable to some voltage. This is a combination of the need to deliver that voltage places, and the need to be able to set that voltage to some values, whether it is a variable amount or is a couple of fixed values.”

Open-loop process compensation helps simplify this a bit. “You implement your block the traditional way during the floor planning and place-and-route, but you have to consider that your power grid also has to route the power for the body bias,” Cesana said. “You have to put in a fuse box, like is used to program memory redundancy, and you need some fuses to program the body bias generator. You need to put the body bias generator in the floorplan to connect it to the grid that you’re supplying the bias of the transistor. Implementation is running the same way. I would say it’s even simpler, because you understand process compensation is reducing the design margins, so all the convergence for closing timing and so on is simpler. Also, you see virtually a faster process, so traditionally you can close your design with more confidence. The design gets smaller, you save some area. Of course you have to pick different PVT corners for the signoff, but nothing else.”

For the closed-loop compensation, a small controller must be added. This can be a state machine. “Then, for the block that you are implementing, there’s no change in the RTL,” Cesana said. “So if the block you are implementing is a microprocessor core, for example, it is implemented the usual way. When you do the floor plan and implementation, you have to put a temperature monitor inside and you have to program the body bias generator. There’s nothing that’s really rocket science. It’s traditional implementation, putting the two or three IPs that are key so there is always a body bias generator to generate the bias voltage for biasing the transistors.”

Biasing at advanced nodes
There are some added quirks at advanced nodes.

“One interesting thing you get at the lower nodes is you have a variability challenge, anyway, which is that your threshold voltage moves around,” said ARM’s Aitken. “In finFET designs, that’s mitigated a little bit. But having all of this device variability means that you have, especially in an adaptive body biasing scheme, a lot of additional things to think about, such as what your margining and signoff process is. When your library has been characterized at a particular Vt point and you’ve just changed it, how do you know that your library is characterized at all for what you are attempting to do?”

There are two schools of thought on that subject. One is that if you’ve characterized your library at several points, then you run your body biasing at these points and sign off as just additional corners. “The other approach would be to say that’s all way too complicated, I’ll do circuit design techniques so these things follow robust paths. As I change the threshold voltage, I essentially get a monotonic change in performance. If I go from a low Vt to a high Vt through body biasing, the circuit slows down. It never speeds up. And for most logic gates, that’s trivial. But for things like flip flops, you actually have to pay attention when you design them or that won’t happen by default. But if you go through that circuit design effort, now you have a case where you can say you don’t care how signoff works, other than the base operating points, but I will dynamically build in this chip the ability to run and ask, ‘Am I at a stable operating point? No, I seem to be too slow. Closed loop gives best power savings, but there is a lot of design complexity involved in making a system that can support that.”

The good news is that today’s tools are much more aware of these issues than they were a decade ago. “Having tool support helps,” Aitken said. “It used to be the case that engineering teams spent all of their time lying to the tools and pretending that these power states didn’t exist so that they wouldn’t crash. But now you can actually use the tools to help you.”


Kev says:

I’m still wondering why I can’t get anyone to admit the complete lack of any power-modeling in SystemVerilog is an issue – you can’t do DVFS let alone body-bias modeling in the standard digital design flows for verification.

UPF just formalizes the “lie”.

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