tag: Magma

Rounding Up Design Corners
By Ed Sperling - 25 Mar, 2010 - Comments: 0

By Pallab Chatterjee With advanced process development occupying the 32nm to 22nm corridor, production SoC and ASIC designs are being built at the 180nm to 45nm nodes. In these processes, the designer has to contend with cross-wafer variation and non-correlated design corners, as well as multiple operation states. This is referred to as multi-corner multi-mode (MCMM) and variation analysis. ... » read more

Experts At The Table: The Reliability Factor
By Ed Sperling - 28 Jan, 2010 - Comments: 0

Low-Power Engineering sat down to discuss reliability with Ken O’Neill, director of high reliability product marketing at Actel; Brani Buric, executive vice president at Virage Logic; Bob Smith, vice president of marketing at Magma, and John Sanguinetti, chief technology officer at Forte Design Systems. What follows are excerpts of that conversation. LPE: Is a more complex supply chain cau... » read more

Experts At The Table: The Reliability Factor
By Ed Sperling - 22 Jan, 2010 - Comments: 0

Low-Power Engineering sat down to discuss reliability with Ken O’Neill, director of high-reliability product marketing at Actel; Brani Buric, executive vice president at Virage Logic; Bob Smith, vice president of marketing at Magma, and John Sanguinetti, chief technology officer at Forte Design Systems. What follows are excerpts of that conversation. LPE: As we push to the next process nod... » read more

Combining Power And Synthesis
By Ann Mutschler - 14 Jan, 2010 - Comments: 0

By Ann Steffora Mutschler Each passing design node shrinks electronic designs ever smaller and more complex, which has made power management a critical design priority – even in the synthesis step in the design flow. Synthesis has always been an integral part of the design process, particularly at the RTL level. But as chip design has become more complicated, the need to raise the pro... » read more

Experts At The Table: The Reliability Factor
By Ed Sperling - 04 Jan, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss reliability with Ken O’Neill, director of high reliability product marketing at Actel; Brani Buric, executive vice president at Virage Logic; Bob Smith, vice president of marketing at Magma, and John Sanguinetti, chief technology officer at Forte Design Systems. What follows are excerpts of that conversation. LPE: Do chips become ... » read more

Slow Start To Software-As-A-Service
By Pallab Chatterjee - 17 Dec, 2009 - Comments: 0

By Pallab Chatterjee Can software as a service (SaaS) really work in the SoC design tools world? While many of the large EDA vendors continue to experiment with it, the future of this model isn’t especially promising. This is contrary to the overall trend among big software makers, which even in the large enterprise applications space are finding success with SaaS and the related cl... » read more

Making DFM Work Better
By Ann Mutschler - 17 Dec, 2009 - Comments: 0

By Ann Steffora Mutschler At 65nm, design for manufacturing optimization and analysis has mostly been an afterthought. At 40nm and beyond, DFM has been pushed well up into the design phase. There are good reasons for this shift. What emerged at the 65nm node were signoff tools that understand manufacturing used in semiconductor design, said Manoj Chako, a product director for digital si... » read more

Synthesis: Next Steps In SoC Design
By Ed Sperling - 17 Dec, 2009 - Comments: 0

Five experts sound off to System-Level Design on the state of synthesis and what's needed in the future: Shawn McCloud, product line director for Catapult C Synthesis at Mentor Graphics; Chris Eddington, director of marketing for system-lvel products at Synopsys; Brett Cline, VP of marketing at Forte Design Systems; Andy Biddle, director of business development at Magma and Sanjiv Kaul, executi... » read more

5 Reasons For Change
By Ed Sperling - 04 Dec, 2009 - Comments: 0

One of the most intriguing trends to watch these days is in the area of diversification and differentiation. As we emerge from the worst downturn in the history of semiconductor design—in fact, the only time EDA has ever shown negative numbers other than accounting changes—companies are looking for new avenues of revenue growth that are significantly different than where they drew their r... » read more

The FPGA Alternative
By Various Writers - 31 Oct, 2009 - Comments: 0

By Geoffrey James Until a few years ago, SoC designers focused almost exclusively on ASICs. While it was theoretically possible to create an SoC design for an FPGA, the programmable chips were too bulky and pricey to be useful for much more than prototyping. Today, however, designers are increasingly turning to FPGAs for their SOC targets for production systems. Why the sudden upsurge in So... » read more

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