tag: magnetic tunnel junctions

The Impact of Magnetic Fields On STT-MRAM Operations
By Technical Paper Link - 29 Oct, 2024 - Comments: 0

A technical paper titled "Impact of external magnetic fields on STT-MRAM" was recently published by researchers at Univ. Grenoble Alpes, Everspin, GlobalFoundries, imec, et al. Abstract "This application note discusses the working principle of spin-transfer torque magnetoresistive random access memory (STT-MRAM) and the impact that magnetic fields can have on STT-MRAM operation. Sources of... » read more

Research Bits: Sept. 24
By Jesse Allen - 24 Sep, 2024 - Comments: 0

Modeling negative capacitance Researchers from Lawrence Berkeley National Laboratory developed an open-source 3D simulation framework capable of modeling the atomistic origins of negative capacitance in ferroelectric thin films at the device level. When a material has negative capacitance, it can store a greater amount of electrical charge at lower voltages. The team believes the FerroX fra... » read more

MTJ-Based CRAM Array
By Technical Paper Link - 01 Aug, 2024 - Comments: 0

A new technical paper titled "Experimental demonstration of magnetic tunnel junction-based computational random-access memory" was published by researchers at University of Minnesota and University of Arizona, Tucson. Abstract "The conventional computing paradigm struggles to fulfill the rapidly growing demands from emerging applications, especially those for machine intelligence because ... » read more

Guidelines For A Single-Nanometer Magnetic Tunnel Junction (MTJ)
By Technical Paper Link - 06 Feb, 2024 - Comments: 0

A technical paper titled “Single-nanometer CoFeB/MgO magnetic tunnel junctions with high-retention and high-speed capabilities” was published by researchers at Tohoku University, Université de Lorraine, and Inamori Research Institute for Science. Abstract: "Making magnetic tunnel junctions (MTJs) smaller while meeting performance requirements is critical for future electronics with spin-... » read more

VCMA-Controlled MTJ Devices For Probabilistic Computing Applications
By Technical Paper Link - 03 Oct, 2023 - Comments: 0

A technical paper titled “Probabilistic computing with voltage-controlled dynamics in magnetic tunnel junctions” was published by researchers at Northwestern University, University of Messina, Western Digital Corporation, and Universitat Jaume I. Abstract: "Probabilistic (p-) computing is a physics-based approach to addressing computational problems which are difficult to solve by convent... » read more

Feasibility of Using Domain Wall-Magnetic Tunnel Junction for Magnetic Analog Addressable Memories
By Technical Paper Link - 23 Mar, 2023 - Comments: 0

A new technical paper titled "Domain Wall-Magnetic Tunnel Junction Analog Content Addressable Memory Using Current and Projected Data" was published by researchers at UT Austin and Samsung Advanced Institute of Technology (SAIT). Abstract "With the rise in in-memory computing architectures to reduce the compute-memory bottleneck, a new bottleneck is present between analog and digital conver... » read more

MTJ-based Circuits Provide Low-Cost, Energy Efficient Solution For Future Hardware Implementation in SC Algorithms
By Technical Paper Link - 30 Dec, 2022 - Comments: 0

A review paper titled "Review of Magnetic Tunnel Junctions for Stochastic Computing" was published by researchers at University of Minnesota Twin Cities. Funding agencies include Semiconductor Research Corporation (SRC), CAPSL, NIST, DARPA and others. Abstract: "Modern computing schemes require large circuit areas and large energy consumption for neuromorphic computing applications, such as... » read more

Testing Embedded MRAM IP For SoCs
By Synopsys - 11 Mar, 2020 - Comments: 0

The challenges of embedded memory test and repair are well known, including maximizing fault coverage to prevent test escapes and using spare elements to maximize manufacturing yield. With the surge in availability of promising non-volatile memory architectures to augment and potentially replace traditional volatile memories, a new set of SoC level memory test and repair challenges are emerging... » read more

Power/Performance Bits: Jan. 22
By Jesse Allen - 22 Jan, 2019 - Comments: 0

Efficient neural net training Researchers from the University of California San Diego and Adesto Technologies teamed up to improve neural network training efficiency with new hardware and algorithms that allow computation to be performed in memory. The team used an energy-efficient spiking neural network for implementing unsupervised learning in hardware. Spiking neural networks more closel... » read more

Can Graphene Be Mass Manufactured?
By Katherine Derbyshire - 18 Oct, 2018 - Comments: 3

Since the isolation of graphene in 2004, the high mobility and unique transport properties of 2-dimensional semiconductors have tantalized physicists and materials scientists. Their in-plane carrier transport and lack of dangling bonds potentially can minimize line/edge scattering and other effects of extreme scaling. While 2-D materials cannot compete with silicon at current device dime... » read more

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