Can Graphene Be Mass Manufactured?

Numerous questions surface about whether 2D materials are the best choice for extreme scaling, and so far there are few answers.


Since the isolation of graphene in 2004, the high mobility and unique transport properties of 2-dimensional semiconductors have tantalized physicists and materials scientists. Their in-plane carrier transport and lack of dangling bonds potentially can minimize line/edge scattering and other effects of extreme scaling.

While 2-D materials cannot compete with silicon at current device dimensions, their performance may degrade less quickly as feature sizes shrink. According to Iuliana Radu, distingished member of the technical staff at Imec, 2-D semiconductors may be the only alternative for sub-15 nm devices.

But 2-D semiconductors also offer a vivid demonstration of the large gap between simulations and laboratory experiments, and from there to devices that can be manufactured by the billions using existing fab infrastructure. There is no clear path to consistent fabrication of 2-D single crystals at this time, Radu noted. Nor are there clear integration paths to achieve stable, repeatable device performance, or processes of record for such fundamental operations as doping and contact formation.

Van der Waals forces build nano sheet stacks
The obstacles to 2-D device development begin with the fabrication of the materials. Graphene was first isolated through mechanical exfoliation, a fancy name for a fairly crude procedure in which single layers are pulled from a bulk sample using adhesive tape. The difficulties inherent in scaling that method to hundreds, much less billions of devices, should be obvious.

One alternative, electrochemical intercalation, infiltrates an inert molecule into a chemical vapor deposition film, chemically isolating the top layer while continuing to use the substrate for mechanical support. Another depends on atomic layer deposition of individual layers, followed by a passivation layer. Layer-by-layer deposition methods can be used to construct van der Waals heterostructures, in which a stack is held together by van der Waals forces while each layer retains its 2-D character.

The properties of van der Waals heterostructures depend on the number of layers, their composition, and the twist angle between them, giving designers wide latitude to achieve the behavior they want. The twist angle in particular can be used to impose long-range periodicity in the absence of three-dimensional crystalline structures.

Moreover, as demonstrated with stacked MoS2 monolayers, the number of layers can define the bandgap of the structure. The coefficients of thermal expansion of the substrate and of individual layers can be tuned to control strain, further adjusting the electrical properties.

When building such structures, though, it’s important to remember that 2-D semiconductors are not a single material, but an entire class of compounds. Conventional III-V and II-VI semiconductors share many structural and electrical characteristics with silicon, germanium, and each other. So materials scientists can vary semiconductor composition as needed to tune the band gap, lattice parameters, and other properties without dramatic changes to the overall integration scheme.

Two-dimensional semiconductors, in contrast, come from different parts of the periodic table. They have different electrical properties, different lattice structures, and different chemical characteristics.

Toward 2-D devices
For example, black phosphorus offers high mobility, but it is unstable in both air and water. Researchers have attempted to turn its need for layer transfer-based fabrication techniques into a virtue, pointing out that low-temperature processes reduce the impact of thermal expansion and lattice mismatch between the semiconductor and the substrate.

Nicolò Oliva, a graduate student at École Polytechnique Fédérale de Lausanne, and his colleagues transferred exfoliated black phosphorus to a prepared substrate with embedded silver or gold electrodes, then passivated the structure with boron nitride followed by an Al2O3 dielectric. In these devices, the contact work function determined the gate polarity, with gold contacts favoring holes and silver favoring electrons.

The gate and drain voltage can be used to modulate the Fermi level and band alignments. Performance was promising, with a 70 mV/decade sub-threshold swing. But making such a device in large quantities is sure to be challenging.

Boron nitride, used as a passivating layer for black phosphorus and as a dopant for graphene, has also attracted attention as a 2-D semiconductor in its own right. One group deposited hexagonal boron nitride directly onto cobalt and iron electrodes. In such magnetic tunnel junctions, among the building blocks of spintronics, hBN serves as the tunneling barrier between cobalt and iron. Switching the polarities of magnetic domains changes the height of the tunneling barrier, causing the device to behave as a magnetometer.

The last group of 2-D semiconductors, the dichalcogenides, are reasonably stable and can be fabricated by such relatively mature processes as chemical vapor deposition. Unfortunately, Tarun Agarwal, a postdoctoral researcher at ETH Zurich, along with researchers at Imec, reported at last year’s IEDM that simulation results for these materials are relatively poor, with low mobility and low drive currents. Competitive devices probably will need to be based on stacks of nanosheets rather than single layers.

As in other stacked nano sheet devices, the number of layers, the components of the stack, and the internal structure of the stack all contribute to device characteristics. As is the case in silicon, double-gate devices offer better electrostatics and better currents than single-gate devices.

Even this brief survey raises as many questions as it answers about the commercial prospects for 2-D semiconductor devices. Yet Imec’s Radu explained that the industry does not appear to have a choice. “Probably, the alternative to 2D semiconductors is changing the computing paradigm,” she said.

The lower effective mass of III-V semiconductors means that direct source-drain tunneling becomes a problem at longer gate lengths than in silicon. Quantum dots provide very little current, limiting their viability for general-purpose logic. Though 2-D materials pose challenges, as well, Radu noted, “there are lots of things we haven’t figured out how to do, but we don’t see any fundamental roadblock.”

She expects any commercial applications of the materials are probably at least 10 years away. For 5nm devices, the decision point is probably five or six years away. She expects it will take that much time for the industry to understand the scaling limitations of 2-D materials and find a realistic path to commercialization.

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Graphene foam


Brett Goldsmith says:

There are today commercial graphene electronics being sold to customers outside of nanotech researchers, and graphene is used in commercial fabs for those products. Even so, the “R&D” market that Imec serves still dominates.

From the point of view of a product designer using graphene, this presentation of an unclear landscape seems to be looking backward rather than forward. The basic research phase should be ended, and it’s time we work on integration with commercial systems.

Katherine Derbyshire says:

While I found a few pointers to the use of graphene as an electrode for flexible devices, I wasn’t able to find any on the use of graphene as a transistor channel in currently shipping commercial devices. Could you post a few links, please?

Anand Chamarthy says:

I agree with Brett that this seems to be looking backward rather than forward. CVD has won out as the scalable growth technique, and several companies continue to make rapid improvements in growth quality/lowering $/m^2.

I also agree with Brett It is now time for integration/commercialization. The recent NGA Conference in Austin was a big step in this direction.

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