Chiplets, Faster Interconnects, More Efficiency


Big chipmakers are turning to architectural improvements such as chiplets, faster throughput both on-chip and off-chip, and concentrating more work per operation or cycle, in order to ramp up processing speeds and efficiency. Taken as a whole, this represents a significant shift in direction for the major chip companies. All of them are wrestling with massive increases in processing demands ... » read more

Using Less Power At The Same Node


Going to the next node has been the most effective way to reduce power, but that is no longer true or desirable for a growing percentage of the semiconductor industry. So the big question now is how to reduce power while maintaining the same node size. After understanding how the power is used, both chip designers and fabs have techniques available to reduce power consumption. Fabs are makin... » read more

Accelerators Everywhere. Now What?


It's a good time to be a data scientist, but it's about to become much more challenging for software and hardware engineers. Understanding the different types and how data flows is the next path forward in system design. As the number of sources of data rises, creating exponential spikes in the volume of data, entirely new approaches to computing will be required. The problem is understandi... » read more

Preparing For Bigger Changes Ahead


The semiconductor industry has undergone a fundamental shift over the past year, and it's one that will redefine chipmaking over the next decade or more. While the focus is still on building the fastest, lowest-power devices, whether that's by shrinking features or packaging them into blazing-fast 2.5D or fan-out configurations, these devices are being customized for specific use cases much ... » read more

CMOS-Embedded STT-MRAM Arrays In 2x nm Nodes For GP-MCU Applications


Perpendicular Spin-Transfer Torque (STT) MRAM is a promising technology in terms of read/write speed, low power consumption and non-volatility, but there has not been a demonstration of high density manufacturability at small geometries. In this paper we present an unprecedented demonstration of a robust STT-MRAM technology designed in a 2x nm CMOS- embedded 40 Mb array. Key features are full a... » read more

Design, Test & Repair Methodology For FinFET-Based Memories


Like any IP block, memories need to be tested. But unlike many other IP blocks, memory test is not as simple as pass/fail. The advent of FinFET-based memories presents new memory test challenges. This white paper covers: The new design complexities, defect coverage and yield challenges presented by FinFET-based memories. How to synthesize test algorithms for detection and diagnosis of Fin... » read more

How Semiconductor IP Became Critical To SoC Design


By Mark Templeton In 1991, I had the good fortune to be a member of the founding team of Artisan Components. We started the company believing that demand was about to appear for semiconductor intellectual property. We had a few data points. We knew that before a company could start a new chip project, they first had to design and verify all kinds of generic building blocks – things like ... » read more

Manufacturing Bits: Dec. 3


Animal robots invade London The London Science Museum will premiere U-CAT, an underwater robot turtle designed to penetrate shipwrecks. In the exhibit, the museum will also showcase several robots that resemble an eel, bat, cheetah cub, tumbleweed, tuna, salamander and other creatures. Meanwhile, built by the Centre for Biorobotics at Tallinn University of Technology, U-CAT’s locomotio... » read more