中文 English

PLANAR: A Programmable Accelerator For Near-Memory Data Rearrangement


Many applications employ irregular and sparse memory accesses that cannot take advantage of existing cache hierarchies in high performance processors. To solve this problem, Data Layout Transformation (DLT) techniques rearrange sparse data into a dense representation, improving locality and cache utilization. However, prior proposals in this space fail to provide a design that (i) scales with m... » read more

IP Requires System Context At 6/5/3nm


Driven by each successive generation of semiconductor manufacturing technology, complexity has reached dizzying levels. Every part of the design, verification and manufacturing is more complicated and intense the more transistors are able to be packed onto a die. For these reasons, the entire system must be taken into consideration as a whole – not just as individual building blocks as could ... » read more

Flexibility Improves Memory Interface Bandwidth


In today’s SoCs, memory is the heart or at least one of the main elements of the design. As such, designing them carefully is paramount to achieving the best bandwidth, performance and power. Performance is very important to be able to access the memory and to trade and store information from different IPs with shared memories or local memories. From the power perspective, every access to... » read more

DDR White Paper


DDR DRAM memory controllers have many competing demands on them. A good memory controller must improve the bandwidth of the memory interface while respecting the latency demands of the CPU, graphics, and real-time DRAM in the system while maintaining compliance with memory bus and on-chip bus standards. The read reorder buffer (RRB) is a silicon-proven architectural enhancement available in... » read more