New Applications Call For New Memory Types

By Sean SK Kang - 20 Jun, 2019 - Comments: 0

The semiconductor industry is on the verge of a transformative computing era driven by Big Data, Artificial Intelligence (AI) and the Internet of Things (IoT). However, achieving the improvements in computing performance and efficiency needed for new AI and IoT applications represent some of the biggest technology challenges the industry has faced. Among the most critical requirements is del... » read more

Playing Into China’s Hands

By Ed Sperling - 13 Jun, 2019 - Comments: 1

The fallout over blacklisting Huawei in particular, and China in general, has set the tone for a nasty global race. But it is almost certain to produce a different result than the proponents of a trade war are expecting. The idea behind tariffs and the blacklisting of Huawei is to starve China of vital technology. So far, the impact has been minimal. Reports from inside of China are equa... » read more

HBM2e Offers Solid Path For AI Accelerators

By Sanjay Charagulla - 13 Jun, 2019 - Comments: 0

Today, AI processors are so blazingly fast that they’re constantly having to wait for data from memory. Unfortunately, with the status quo, memory is just not fast enough to unleash the true performance of those new and highly advancing AI processors. In simple terms, AI processor performance is rapidly growing, and memory is not keeping up. This creates a bottleneck, or what Rambus calls the... » read more

Resetting Serial Memory When A System Failure Occurs

By Paul Hill - 13 Jun, 2019 - Comments: 0

Stability is an important consideration in embedded design, but electronic systems can suffer malfunctions triggered by a myriad of root causes. These include poor signal integrity, power spikes, software errors, and erroneous user interaction, just to name a few. These anomalies, in turn, can lead to inconsistent system operation or can even cause the system to hang. Although the list of po... » read more

HBM2 Vs. GDDR6: Tradeoffs In DRAM

By Ed Sperling - 13 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to talk about new DRAM options and considerations with Frank Ferro, senior director of product management at Rambus; Marc Greenberg, group director for product marketing at Cadence; Graham Allan, senior product marketing manager for DDR PHYs at Synopsys; and Tien Shiah, senior manager for memory marketing at Samsung Electronics. What follows are excerpts of th... » read more

Accurate Error Bit Mode Analysis Of STT-MRAM Chip With A Novel Current Measurement Module

By Advantest - 11 Jun, 2019 - Comments: 0

Authors: (Advantest) Ryo Tamura, Ibuki Mori Naoyoshi Watanabe; (Tohoku University) Hiroki Koike, Tetsuo Endoh. A novel memory test system is needed for future STT-MRAM mass production that supports error bit analysis and its mode categorization on STT-MRAM chip measurement, as STTMRAM cell’s switching is a probabilistic phenomenon based on quantum mechanics. In order to meet this requireme... » read more

Controlling Variability And Cost At 3nm And Beyond

By Ed Sperling - 22 May, 2019 - Comments: 1

Richard Gottscho, executive vice president and CTO of Lam Research, sat down with Semiconductor Engineering to talk about how to utilize more data from sensors in manufacturing equipment, the migration to new process nodes, and advancements in ALE and materials that could have a big impact on controlling costs. What follows are excerpts of that conversation. SE: As more sensors are added int... » read more

Engineering The Signal For GDDR6

By Shawn Nikoukary - 09 May, 2019 - Comments: 0

DDR1 through DDR3 had their challenges, but speeds were below one gigabit and signal integrity (SI) challenges were more centered around static timing and running pseudo random binary sequence (PRBS) simulations. Now, with GDDR6, we are working on 16 to 20 gigabits per second (Gbps) signaling and even faster in the near future. As a result, engineering the signal for GDDR6 will require careful ... » read more

Latency Under Load: HBM2 vs. GDDR6

By Ed Sperling - 09 May, 2019 - Comments: 0

Steven Woo, Rambus fellow and distinguished inventor, explains why data traffic and bandwidth are critical to choosing the type of DRAM, options for improving traffic flow in different memory types, and how this works with multiple memory types. Related Video GDDR6 - HBM2 Tradeoffs Why designers choose one memory type over another. Applications for each were clearly delineate... » read more

Power/Performance Bits: May 6

By Jesse Allen - 06 May, 2019 - Comments: 0

Compressing objects Computer scientists at MIT propose a way to improve data compression in memory by focusing on objects rather than cache lines. "The motivation was trying to come up with a new memory hierarchy that could do object-based compression, instead of cache-line compression, because that's how most modern programming languages manage data," said Po-An Tsai, a graduate student at... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.