tag: Mentor Graphics

Experts At The Table: Yield And Reliability Issues With Integrating IP
By Ed Sperling - 08 Jan, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of integrating IP in complex SoCs with Juan Rey, senior director of engineering at Mentor Graphics; Kevin Yee, product marketing director for Cadence’s SoC Realization Group; and Mike Gianfagna, vice president of marketing at eSilicon. What follows are excerpts of that conversation. SE: Do we need to move to subsystems or more restri... » read more

Blog Review: Jan. 8
By Ed Sperling - 08 Jan, 2014 - Comments: 0

How do you choose an embedded operating system—and do you even need one? Mentor’s Colin Walls looks at the options, and the reason why there are no simple answers. Cadence’s Richard Goering has evidence that Facebook is gaining in popularity for engineer. He’s not the first person to recognize this shift, but the big unanswered questions are, ‘What’s the average age of those use... » read more

Routing Closure Challenges At 28nm And Below
By Jean-Marie Brunet - 03 Jan, 2014 - Comments: 1

As I described in my last article, the gap between router tech files and signoff rule decks at 28 nm and below is generating some serious impacts on tapeout schedules. The mismatch between the router’s simplified tech file and the complex rules that represent the intricate manufacturing requirements at these leading-edge nodes means designs that come from the router “DRC/DFM-clean” will, ... » read more

Blog Review: Jan. 2
By Ed Sperling - 02 Jan, 2014 - Comments: 0

ARM’s Lori Kate Smith has been scouring the market for cool devices. Her pick: the Epic Giveaway wrist computer for runners. She says the only drawback is the 10-hour battery life, but if you can run that long and still have some juice left in your body you probably need a GPS, instead. Mentor’s J VanDomelen has been tracking orders from the United Arab Emirates’ and its neighbors for ... » read more

When Is Verification Done?
By Ed Sperling - 20 Dec, 2013 - Comments: 0

Verification is becoming much more difficult at 16nm/14nm, driven by the sheer complexity of SoCs, the fact that there is much more to verify, and the impact of physical effects, which now affect what used to be exclusively the realm of functional verification. The questions these changes raise are daunting, and for many engineers rather unnerving. The whole validation, verification and debu... » read more

Plans Vs. Planning
By Jon McDonald - 20 Dec, 2013 - Comments: 0

The end of the year is a good time to look back at what’s happened over the past year, and look ahead to what might happen in the coming one. Two quotes that help my thought process when thinking about the might be coming, “Change is the law of life.” from Kennedy, and “Plans are nothing, but planning is indispensable” from Eisenhower. From my perspective, 2013 has been a good year... » read more

Week In Review: System-Level Design
By Ed Sperling - 20 Dec, 2013 - Comments: 0

Synopsys extended its FPGA prototyping board with a new version that is optimized for IP and subsystems. This is particularly interesting given the fact that Synopsys is one of the largest IP providers and currently sells subsystems based on its ARC processor IP. Among the new features are support for 4 million gates for software development and hardware-software integration, as well as synthes... » read more

Where Is 2.5D?
By Ed Sperling - 19 Dec, 2013 - Comments: 3

After nearly five years of concentrated research, development, test chips and characterization, 2.5D remains a possibility for many companies but a reality for very few. So what’s taking so long and why hasn’t all of this hype turned into production runs instead of test chips? Semiconductor Engineering spent the past two months interviewing dozens of people on this subject, from chipmakers ... » read more

Industry Restructures Around Cost
By Ed Sperling - 19 Dec, 2013 - Comments: 1

Talk to any semiconductor executive these days about what’s next for their company and you’ll probably encounter the same perspective—cost will drive future design decisions. Dig a little further, however, and you’ll find no consistent strategy for reducing that cost. While the industry has three very viable solutions for improving the power and performance characteristics of SoCs—... » read more

Making Modeling Less Unpleasant
By Brian Bailey - 19 Dec, 2013 - Comments: 1

How many times did your mother tell you to take your medicine? You knew two things: a) it would be unpleasant and b) it would be worth the few seconds of unpleasantness because of the benefits it would provide. It appears as if the electronics industry has the same issue with modeling. We talk about the benefits that having a system-level model would have — the ability to explore system archi... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy