tag: Mentor Graphics

Like Oil And Water
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ann Steffora Mutschler For years, the promise and allure of a concurrent design methodology included talk of models, high-level synthesis, virtual prototyping and other system-level technologies all peacefully coexisting in a single design methodology. While it sounds like a good idea, the model-based design approach hasn’t mixed well with the virtual prototype approach. And at l... » read more

Measuring RTOS Performance: What? Why? How?
By Various Writers - 27 Sep, 2012 - Comments: 0

In the world of smart phones and tablet PCs memory might be cheap, but in the more constrained universe of deeply embedded devices, it is still a precious resource. This is one of the many reasons why most 16- and 32-bit embedded designs rely on the services of a scalable real-time operating system (RTOS). An RTOS allows product designers to focus on the added value of their solution while dele... » read more

The Good And Bad Of Models
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ann Steffora Mutschler Driven by fierce competition and the fact that socket decisions are made long before silicon is manufactured, semiconductor companies today ship models and virtual prototypes to their OEMs very early in hopes of locking in the socket. Admittedly, this has been happening for some time, but due to complexity and the need for flexibility of models and virtual platf... » read more

A Hybrid Model/Pattern-Based OPC Approach For Improved Consistency And TAT
By Various Writers - 20 Sep, 2012 - Comments: 0

As the technology advances, OPC run time turns to be a big concern, and a great deal of our effort is directed toward speeding up the litho operations. In addition, the OPC simulation consistency sometimes deteriorates, which is a critical issue—especially for anchor features. On the other hand, full-chip designs usually comprise large arrays of basic cells, used by OPC engineers to tune OPC ... » read more

Power Budgets: Where Is The Low-Hanging Fruit?
By Ed Sperling - 15 Sep, 2012 - Comments: 0

Low-Power Engineering looks for the best ways to cut power for a reasonable cost with Mentor Graphics, Synopsys, Apache Design Solutions, Oasys Design Systems and Xilinx. [youtube vid=Gqoenm00Mso] » read more

The Double Whammy
By Ed Sperling - 13 Sep, 2012 - Comments: 0

By Ann Steffora Mutschler Given that at 40nm and below every [getkc id="81" kc_name="SoC"] has some mixed-signal content, combined with the fact that power awareness is top priority no matter what the target application is, design teams and verification engineers are grappling with tremendous challenges just to get a chip to yield. “For verification engineers and for designers, this is a ... » read more

Blurring The Lines At The OS Level
By Ed Sperling - 13 Sep, 2012 - Comments: 0

By Ed Sperling Picking an operating system—or choosing not to use an operating system—is becoming as complex a decision as choosing which IP to use in an SoC. Even decisions that sound straightforward may have ramifications on the total system power budget or performance, requiring them to be an integral part of the overall architectural process. But the choice of operating systems, as ... » read more

Improving Reliability
By Dina Medhat - 13 Sep, 2012 - Comments: 0

By Dina Medhat Advanced IC designs implement complex strategies to minimize static and dynamic power. Mixed-signal designs typically require different supply voltages for the analog and digital portions of the design, and even all-digital ICs can have many power domains and operating voltages. Typically, some signal lines cross from one domain to another and special interfaces and “voltage p... » read more

Experts At The Table: Stacked Die Reality Check
By Ed Sperling - 10 Sep, 2012 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Sunil Patel, principal member of the technical staff for package technology at GlobalFoundries; Steve Pateras, product marketing director at Mentor Graphics; Steve Smith, senior director of platform marketing at Synopsys; Thorsten Matthias, business development director at EVGroup; and Manish Ranjan, vice president of market... » read more

Computational Lithography
By Various Writers - 31 Aug, 2012 - Comments: 0

Computational lithography has become an integral part of design since the 130 nm process node. New techniques continue to be developed to extend the steady node shrink year after year. To download this white paper, click here. » read more

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