tag: Mentor Graphics

Playing The Voltage Game
By Ed Sperling - 01 Dec, 2011 - Comments: 0

y Ed Sperling Scaling down the voltage to boost battery life and cut energy costs has always been considered the best option, but it’s getting more difficult at advanced nodes and in stacked die packages. The key problems are noise and leakage. Lowering the voltage exacerbates both of them, forcing a rethinking of the whole design process starting at the architectural level and continuing... » read more

Experts At The Table: Stacked Die And The Supply Chain
By Ed Sperling - 26 Nov, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss the effects of stacking die on the supply chain with Stephen Pateras, production marketing director for silicon test at Mentor Graphics; Javier DeLaCruz, director of manufacturing technology at eSilicon; Colin Baldwin, director of marketing at Open-Silicon; Charles Woychik, director of marketing and technical analysis... » read more

Build It Faster
By Ed Sperling - 17 Nov, 2011 - Comments: 0

By Ed Sperling Hitting market windows with IC designs has always been a struggle, but the race to the finish line is becoming more critical—and much more difficult. The reason: Market windows themselves are shrinking. Products that used to stick around for years may now only last for months, replaced by newer versions that offer either better performance or lower power. In many cases, par... » read more

Dinner Talk
By Jon McDonald - 17 Nov, 2011 - Comments: 0

By Jon McDonald Recently at dinner we were discussing a new video game my son wanted. My wife and I were less than thrilled with the game due to some of the adult themes I had seen in the reviews. As my son was trying to convince us that it was an acceptable game he fell back on the old standard justification: “All my friends are playing it!” This is one of the poorest reasons for anyt... » read more

Five Important Changes That Will Affect Power
By Ed Sperling - 03 Nov, 2011 - Comments: 0

By Ed Sperling So far most of the energy savings in SoCs have been achieved using two main approaches—turning off most of the chip most of the time, and changing the materials used to insulate against current leakage. Over the next few years, changes to designs will be more radical, encompass more pieces of a bigger system, and they will be orders of magnitude more effective. From a marke... » read more

Energy Vs. Power
By Ed Sperling - 03 Nov, 2011 - Comments: 0

By Ann Steffora Mutschler In the quest to optimize an SoC for both power and energy efficiency many variables come into play. Target application, use cases, processor choice and amount of memory among other specifications all figure into the optimization equation. As discussed in Part 1 of this series, energy and power are different entities and must be understood distinctly from each other... » read more

Innovation At The Core
By Barry Pangrle - 03 Nov, 2011 - Comments: 0

By Barry Pangrle A number of next-generation ARM-based multi-core systems are starting to show up in the press. Nvidia has released information on its upcoming Tegra 3 (also known as “Kal El”). At last week’s ARM Techcon in Santa Clara, ARM gave several presentations around its Cortex-A7 (Kingfisher) and Cortex-A15 (Eagle) architectures and collectively about its big.LITTLE strategy. Qua... » read more

More EMI Mitigation
By Ann Mutschler - 03 Nov, 2011 - Comments: 0

With electromagnetic interference a major design challenge today in any product that sends or receives a signal, determining how to lessen the impact of this phenomenon was addressed to a large extent in my article, “EMI Cuts a Wide Swath,” but there are a few additional techniques that are important to highlight. Erick Olsen, marketing director at NXP explained that higher performance c... » read more

The Next SoCs
By Ed Sperling - 20 Oct, 2011 - Comments: 0

By Ed Sperling The number of changes that will hit the IC market over the next few years is almost staggering by any standard—past or present. In addition to the relentless pressure of Moore’s Law, there will be new materials, new structures, and new models for developing and packaging chips. System-Level Design asked executives from across the SoC ecosystem what will change, what’s d... » read more

VIP: Behind The Velvet Rope
By Ed Sperling - 20 Oct, 2011 - Comments: 0

By Ann Steffora Mutschler Some years ago, as engineering teams began to incorporate more protocols into designs and as those protocols grew in sophistication and complexity in order to deliver additional performance, the verification task grew concurrently. At the same time, the design IP market was growing as complexity drove re-use of components, along with verification components—most com... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy