tag: Mentor Graphics

3D Stacking: A Reality Check
By Ed Sperling - 28 Jul, 2011 - Comments: 0

By Ed Sperling The first 2.5D and 3D chips are expected to arrive next year, with the mainstream chip market expected to follow in 2013. While this trend already has seen its share of hype, stacked die—whether through a series of TSVs in true 3D or through an interposer layer in 2.5D—is as real as Moore’s Law. In fact, it’s a direct result of Moore’s Law. But unlike the progres... » read more

Start The Revolution
By Jon McDonald - 28 Jul, 2011 - Comments: 0

By Jon McDonald “Know thyself.” That advice is promoted in so many different forms it's hard to know where it started. I have been involved in a number of projects recently in which these words would have greatly simplified the project flow. “Simplified” is probably not quite the right word. The issue in this case is not to simplify the project, but to properly understand, characterize... » read more

Debugging Double Patterning without Getting Double Vision
By David Abercrombie - 27 Jul, 2011 - Comments: 1

By David Abercrombie Given that my last couple of blogs on double patterning (DP) might have scared you to death, I figured it was time to bring you some good news. It is unavoidably true that double patterning layout constraints at 20nm and below are going to require changes in all aspects of the design flow, but Mentor Graphics (and, I am sure, the rest of the EDA industry) is working very... » read more

Experts At The Table: Multi-Foundry Strategies
By Ed Sperling - 26 Jul, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing and Design sat down with Walter Ng, vice president of the IP ecosystem at GlobalFoundries; John Murphy, director of strategic alliances marketing at Cadence; Michael Buehler-Garcia, director of Calibre design solutions marketing at Mentor Graphics; Bob Smith, vice president of marketing and business development at Magma, and Linh Hong, vice president ... » read more

Design For Power Methodology
By Ed Sperling - 21 Jul, 2011 - Comments: 0

By Ann Steffora Mutschler It is rare to find an advanced chip today that has not been designed considering power from the very earliest point. In fact, it is safe to say that power is the No. 1 priority, or a close No. 2. But to achieve the highest performance for a low-power design, a design-for-power methodology is necessary, comprised of the capabilities to implement power in the most ef... » read more

Building A Better CMOS FET
By Barry Pangrle - 21 Jul, 2011 - Comments: 0

By Barry Pangrle SEMICON West was held last week in San Francisco and I had the opportunity to attend the Emerging Architectures session. Serge Biesemans, vice president of process technology at Imec, gave a nice overview presentation on FinFETs. From a power and performance standpoint, we’ve seen some early pre-production information released from Intel that I briefly discussed here. Serge�... » read more

Blog Review: July 20
By Ed Sperling - 20 Jul, 2011 - Comments: 0

By Ed Sperling Synopsys’ Eric Huang pays a visit to the Microsoft Store and finds a really smart salesperson who seems to know just about everything there is to know about the products for sale. And yes, that is somewhat unexpected. Cadence’s Jean-Michel Fernandez talks about creating SystemC peripheral models. Fernandez represents Cadence’s Team ESL, which is an interesting developme... » read more

Going With The Flow
By Ed Sperling - 15 Jul, 2011 - Comments: 0

It’s hard to judge things in isolation, but a continuum of acquisitions in the low-power area is proving just how important power considerations have become to hardware and software design, verification and manufacturing flows. Over the past couple of years acquisitions by Synopsys in the virtual prototyping arena, and Mentor Graphics in the test and embedded software area, have included p... » read more

The Challenge of 3D
By Ed Sperling - 06 Jul, 2011 - Comments: 0

Juan Rey, senior director of engineering for Mentor Graphics' Design To Silicon Division, talks about 3D stacking and 3D structures on chips. [youtube vid=YiH5IkxiEHU] » read more

A Smart Filling Solution Yields Multiple Benefits
By Mentor Graphics Staff Writers - 01 Jul, 2011 - Comments: 0

By Jeff Wilson, A return on investment doesn’t happen until customers actually buy your product, so the most fundamental goal for designers is getting their designs to market. While there are numerous steps along the way, one task that must be performed is adding fill to the design. Fill is like design rule checking (DRC)—it’s not an optional step, because it is needed to ensure the manu... » read more

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