tag: Mentor Graphics

$23 For A Deli Sandwich?
By Jon McDonald - 28 Apr, 2011 - Comments: 0

By Jon McDonald I have talked to a number of people recently about the justification for investing in an ESL methodology. “What’s the ROI?” is a question I hear fairly often. I’m currently on vacation in New York City with my family, and during the trip I’ve realized just how subjective ROI can be. What’s the ROI on a $23 deli sandwich? At home I’d never think about paying tha... » read more

Experts At The Table: Yield Issues
By Ed Sperling - 22 Apr, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss yield with Amiad Conley, technology marketing manager for yield and process control at Applied Materials; Cyrus Tabery, senior member of the GlobalFoundries technical staff for lithography development and DFM; Brady Benware, engineering manager for diagnosis and yield at Mentor Graphics, and Ankush Oberai, general man... » read more

ESL Power Optimization Flow Requires Ecosystem
By Ann Mutschler - 14 Apr, 2011 - Comments: 0

The issue of power optimization today is very painful for many chip architects who are tasked with determining, meeting and holding to a tight power envelope. Questions concerning how well and to what extent power can truly be understood at the architectural level, let alone optimized, are the subject of debate. The ITRS’s most recent projection provides some insight as to current market d... » read more

Rationalization For Power
By Ed Sperling - 14 Apr, 2011 - Comments: 0

By Ed Sperling Power budgets are becoming almost universally problematic. What used to be a unique headache for the cell-phone market has evolved into an ugly migraine that now includes everything with a battery—and increasingly even those devices that rely on a plug. The result is a cascade of effects that are widespread and growing. And while the drivers of this effort vary widely from ... » read more

Emulation Power
By Barry Pangrle - 14 Apr, 2011 - Comments: 0

By Barry Pangrle Power budgets and the characteristics of the underlying process technologies have limited the clock speeds of the processors often found in large compute farms for simulation over the past six years, but the designs under test have followed Moore’s Law and have kept growing larger at an exponential rate. Processor designers have added more cores per chip to increase the p... » read more

Wanted: ESL Power Design Flow
By Ann Mutschler - 14 Apr, 2011 - Comments: 0

In order to truly incorporate understanding of power at a higher-than-RTL level of abstraction, a new design flow is needed—and it won’t come from just one vendor. Apache believes that tool flow must contain ESL simulation, ESL synthesis to RTL along with RTL power analysis using ESL simulation results. The company maintains that this very approach has been demonstrated successfully by w... » read more

Experts At The Table: Yield Issues
By Ed Sperling - 10 Apr, 2011 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down to discuss yield with Amiad Conley, technology marketing manager for yield and process control at Applied Materials; Cyrus Tabery, senior member of the GlobalFoundries technical staff for lithography development and DFM; Brady Benware, engineering manager for diagnosis and yield at Mentor Graphics, and Ankush Oberai, general man... » read more

The Quest For A Better IP Integration Methodology
By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Ed Sperling With the amount of IP in SoC designs now hitting an estimated 70% to 90%, companies are scrambling to figure out a way to more consistently integrate that IP and to test that it will work as expected. This is easier said than done, however, for a number of reasons: There are numerous types of IP, ranging from I/O to logic and memory. Not all IP is of equal quality. ... » read more

Keeping Up With Complexity
By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Ed Sperling There are two schools of thought in designing complex SoCs. One says that increasing complexity requires a higher level of abstraction. The other says providing enough detail to get the design right is the only effective way to do it. There are staunch proponents of both approaches, but what has been missing are bridges to tie the higher level of abstraction to the more labo... » read more

3D ICs: No Simple Answers
By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Pallab Chatterjee Just how ready is the semiconductor industry for stacked die? That was the subject of a recent panel discussion involving ARM, Atrenta, Xilinx, Samsung and Mentor Graphics. The reasoning behind 3D stacking is becoming clearer at each node. I/O count and delay times are forcing different configurations, but the time frames for these changes and the gating constraints are... » read more

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